Overview

Final Projects  (2012)

• Each team will be assigned a project by the instructor
• Each team will be assigned several negative impedance circuits to design, simulate, tape-out, fabricate, and test in MOSIS  0.5 micron 
• The final project will be worth 35% of the total course grade
• Any student missing more than one class session will forfeit 20% of final project grade
• Any student missing the final demonstration will forfeit 20% of final grade
• At the sole dscretion of the instructor, any student may be assigned to a separate individual chip design project, if they are not contributing to their team effort
  
• Any group missing any design review below will forfeit 25% of final project grade
  
• All layouts MUST be done in Cadence Layout XL and all simulations must be in Cadence ADEXL and ADS.  Avoid using "L" or "GXL" versions, use "XL" versions of the software to avoid incompatible designs.
  

• Grade weighting and schedule:
• Nov. 12: Schematic/simulation design review: 15%
• Nov. 26: Layout design review: 15%
• Dec 3: Final demonstration: 30%
• Dec 10: Final report 40%

• Project Assignments
  
• Negative impedance converters (NIC) negate an impedance (Z becomes -Z) and negative impedance inverters (NII) negate and invert the impedances (Z becomes -1/Z).
• All designs should fit in the lower half of the chip, and only use pins 21 to 30 (ask if needing more).
• All designs must be measured (and stable!) using a 50-ohm test system.
• Required operating frequency range: All designs should accomplish the required negative capacitance or negative inductance to within +/-15 percent of the low frequency nominal "flat" value from 50 MHz up to 500 MHz minimum (preferably  up to 1 GHz).   The resistive component of the reactance should also remain within +/-15 percent of the low frequency nominal "flat" value from 50 MHz up to 500 MHz minimum.
• All circuits must be tested for proper impedance from  at least 0.01 GHz to 2 GHz.  Resistance R and reactance X, must be extracted and plotted from S-parameters.
  
• All circuits must be tested for proper capacitance and inductance  from  at least 0.01 GHz to 2 GHz.  Capacitance C and inductance L, must be extracted and plotted from S-parameters.
• All circuits must be tested for instability.  Use a current source and short impulse to test for instability, adjusting the current to produce a voltage impulse typically of the order of 0.1 volt.  Test over a time-domain range of several hundred ns for high-frequency instability, and 10 ms for low-frequency instabilities.
• All single-ended designs should only require Vdd 5 volt power, ground, a single unbiased input pin for the negative impedance, and a possible tuning pin (such tuning pin must default to some value when the tuning pin is open circuit or unused).    An even bettter single-ended design would only require Vdd and ground, where the negative impedance would be seen at the Vdd pin and tunable by changing Vdd.
• All differential designs should only require Vdd 5 volt power, ground, a pair of biased input pins (with default dc bias for ac-coupled pins) for the negative impedance, and a possible tuning pin (such tuning pin must default to some value when the tuning pin is open circuit or unused).    Pay careful attention to the 2-port measurement methods of a differential input, as described in the paper by Stephane Wloczysiak.
• For stable test/measurement, some designs may require a "swamping capacitor" or "swamping inductor" adding positive reactance that makes the net impedance positive.  See section III of the paper by White, C.R.; May, J.W.; Colburn, J.S..  Other designs may have simultaneous negative resistance and reactances that allow stable measurement without swamping.  If your design requires swamping, an open-circuit jumper in the design kit may be useful (it can be scratched to make connections).  Some designs may require a dc path to ground, and may become unstable when dc decoupling is used.  It may take some time towork around such issues.  If you encounter such problems, see the slides by Sussman for thoughts on open-circuit stable and short-circle stable rearrangements of such circuits.  The paper by Stearns may also be useful.
  
• All circuits must be tested for instability.  Use a current source and short impulse to test for instability, adjusting the current to produce a voltage impulse typically of the order of 0.1 volt.  Test over a time-domain range of several hundred ns for high-frequency instability, and 10 ms for low-frequency instabilities.
  
• Do not connect all of your circuits to a single vdd pin, since one bad/oscillating circuit would then cause your whole chip to fail.  For exmple, if your project was to create a negative inductor and a negative capacitor, you should have a separate vdd pin for each circuit so you could disable one of them if it fails or oscillates.
• For designs that come off the chip (are not measured on internal gssg probe points), it would best to add wirebond and package inductances (approx 5 to 8 nH in series) and capacitances (approx 5 pF to ground) in your test circuit simulations.  Do not forget to add these to vdd and ground pins.  Details of proper DIP40 package parasitic inductance and capacitances are at MOSIS.   Consider added capacitance for PC boards.
• For each of the assigned circuits for each team:
• Each of the following designs is just a starting point.  It is up to each team to refine the design to meet all of the objectives outlined above and below.
  
• Place the negative impedance loading/reference capacitors (typically 1 to 4 pF) on-chip, even if it is shown in the test circuit below (move it into the subcircuit of your cell)
• Use the internal gssg pads for the main copies of your design (so we can test high frequencies)
  
• Bring a second copy of each design out to the pins (bring all useful subcircuit pins out) for later debugging purposes and low frequency tests
  
• Downlaod project file RFcourse2012_finalProject_29oct2012_wrk.zip
  
• Team 1 Project: 
• -5 pF cross-coupled pair differential design using "team1" design files topology
• -100 nH single-ended (grounded) design using "team1" design files topology
• Team 2 Project: 
• -5 pF cross-coupled pair differential design using "team2" design files topology
• -100 nH single-ended (grounded) design using "team2" design files topology
• Team 3 Project: 
• -5 pF current conveyor single-ended (grounded) design using "team3" design files topology (example file may have stability issues)
  
• -10 pF single-ended (grounded) design using "team2" design files topologyas starting point, and Sussman slides referenced above
  
• Team 4 Project:
  
• -100 Ohm resistor current conveyor single-ended (grounded) design using "team4" design files topology (example file may have stability issues)
  
• -50 nH single-ended (grounded) design using "team4" design files, by inserting active inductor into current conveyor design

• Technical references/notes
  
• Consult the instructor for project technical questions
• Negative impedance converters (NIC) negate an impedance (Z becomes -Z) and negative impedance inverters (NII) negate and invert the impedances (Z becomes -1/Z).
• Stability is often an issue.  See various papers below.
  
• The following papers are useful starting points for the project:
• Matching Network Design Using Non-Foster Impedances slides by Stephen E. Sussman-Fort, Ph.D., an  excellent primer on impedance converters and impedance inverters, especially slides 11 - 14 nd slide 24 for single-ended (grounded) negative L and C
  
• The current conveyor: history, progress and new results by Sedra, A.S., Roberts, G.W. ;  Gohh, F.  summarizing basic ideas of current conveyors
• A second-generation current conveyor and its applications by Sedra, A.S., Smith, K, how to use current conveyors in impedance converters
  
• Low-power High Bandwidth CMOS Current Conveyor  by Popovic, J. Pavasovic, A. ;  Vasiljevic, D.   where a simple CMOS current conveyor is given in Fig. 2
  
• Gyrator-based biquad filters and negative impedance converters for microwaves by Stephen E. Sussman-Fort  where Fig. 16 and 17 summarizes negative impedance converters, and Fig 19 shows the Meunier negative impedance converter (used for a negative resistance)
  
• A Variable Negative-Inductance Integrated Circuit at UHF Frequencies by White, C.R.; May, J.W.; Colburn, J.S. where Fig. 1 shows a SiGe implementation of a differential negative inductance
  
• The simple CMOS negative capacitance with improved frequency response by Mrkovic, B.; Asenbrener, M. where Figs. 1 and 2 show cross-coupled CMOS method to create negative resistance and negative capacitance
  
• Using a Negative Capacitance to Increase the Tuning Range of a Varactor Diode in MMIC Technology by Svilen Kolev,  Bruno Delacressonnière, and Jean-Luc Gautier  where Fig. 4 shows two FETs and an inductor to create a negative capactance
  
• Wide tunable CMOS active inductor by Reja, M.M., Filanovsky, I.M. ;  Moez, K. by  where Fig. 1 shows simple CMOS active inductors
  
• Non-foster circuits and stability theory  by Stearns, S.D.   where Fig. 2 includes a summary of many topologies.
  
• Feedforward-type parasitic capacitance canceler and its application to 4 Gb/s T/H circuit  by  Sato, T.; Takagi, S.; Fujii, N.; Hashimoto, Y.; Sakata, K.; Okada, H.whereFig. 2 shows a cross-coupled negative impedance converter (NIC)
• Match The Ports Of Differential Devices by Stephane Wloczysiak at Microwaves and RF explains how to compute common mode and differential mode impedance parameters (also referred to as even and odd mode) from 2-port S-parameters
• More Cadence tutorials are at a variety of other websites, (some below support older versions, not the newer version 6)
• http://www.eda.ncsu.edu/wiki/NCSU_EDA_Wiki
• http://www.seas.upenn.edu/%7Eeecad/cadence/cadence.html
• http://www.cadence.com/support/university/Pages/default.aspx
• http://www.cs.utah.edu/cadence/
  
• http://www.cadence.com/support/university/ww_usp.aspx
• http://www.ece.umd.edu/~dilli/research/layout/cadencetutorial/cadencedemo9.html
• http://coefs.uncc.edu/tpweldon/cadenceproductsatunccharlotte/

• Install the final project design kit.
• Move all old designs and design kits out of your ~/cadence6/NCSU16 directory into some safe area for storage
• Update your ~/cadence6/NCSU16/cds.lib to remove all the old links by commenting the lines out (use pound sign at beginning of lines)
• Download the final project design kit:  rf2012finalProj_12nov2012d.zip and unzip into your ~/cadence6/NCSU16 directory
• Update your ~/cadence6/NCSU16/cds.lib to add the new library
• Run the Cadence6/virtuoso software
  
• Before doing anything, rename the library to teamXrf2012finalProj, where teamX is your team number as follows, making sure to check "update instances" (red arrow below)
  

• Then rename the top-level cell teamX_FinalProj2012_top , where teamX is your team number as follows,   making sure to check "update instances" (red arrow below)

• Open your renamed top cell to see the layout and schematic, as shown below
• You MUST USE THE starting design below, and you CANNOT remove/move/change any of the existing parts in this starting design below
  
• Two ground pins are set: pins 10 and 30 (purple arrows below)
• Internal RF probes for calibration are set (yellow circle and arrow below)
• Two sets of gssg internal RF probes are provided (blue arrows below)
• Use these gssg probes to test a differential negative impedance (see technical paper by Stephane Wloczysiak cited above)
  
• Use these gssg probes to test a high frequency version of your circuit (>100 MHz)
  
• A wn50 NFET, a 50 ohm resistor, and a 10k resistor are brought out to the pins to allow characterization of the basic devices after fabrication (red circles and arrow)
  

• Use the standard parts included in the library to save time and to prevent errors in fabrication
  
• In your design:
• You MUST USE the starting design above, and you CANNOT remove/move/change any of the existing parts in this starting design
  
• You must only use standard transistors from the library: wn5, wn50, wp10, wp100
• You must only use standard resistors from the library: R50, R100, R500, R1k, R2k, R10k, etc
• You must only use standard capacitors from the library: C1, C4, C10
• No custom parts are permitted

• Schematic/simulation design review. 
  
• In this design review, you must show successful simulation of your assigned circuits in ADS and Cadence ADEXL/spectre (minimum 50% deduction if you do not demonstrate in Cadence) 
• minimum performance specs to be demonstrated must include:
•  must include Cadence/ADEXL s-parameters,
•  must include Cadence/ADEXL extracted impedance Z, inductance, capacitance and resistance,
  
• must include Cadence/ADEXL  time-domain transient response at critical nodes to demonstrate stability,
  
• must include Cadence/ADEXL extracted differential impedance, inductance, capacitance and resistance for differential circuits

• At the time of this design review, each team must turn in a report that includes:
• A 1-page executive summary of your project
  
• Schematics for the assigned circuits from both ADS and Cadence such as:

    

• Schematics for the test circuits for the assigned circuits from both ADS and Cadence such as:

     

• Simulation results from both ADS and Cadence such as:

    

• Layout design review.
  
• In this design review, you must show successful layout of the cells for your assigned circuits
  
• Must demonstrate layout of your assigned circuits passing DRC check.  
• Must demonstrate layout of your assigned circuits passing LVS. 
• Padframe not yet required for this design review
• At the time of this design review, each team must turn in a report that includes:
  
• A 1-page executive summary of your project
  
• Updated schematics for the assigned circuits from both ADS and Cadence as in the Schematic/simulation design review above
• Updated schematics for the test circuits for the assigned circuits from both ADS and Cadence as in the Schematic/simulation design review above
• Updated Simulation results from both ADS and Cadence as in the Schematic/simulation design review above
• Layouts for the assigned circuits in Cadence Layout XL such as:

• Final demonstration. 
  
• Final files must be turned in to instructor
• Your library must be named teamXrf2012finalProj, where teamX is your team number
  
• Your top level design must be named teamX_FinalProj2012_top, where teamX is your team number
• You must zip your library and give it to the instructor at the beginning of class
• The instructor will run all tests from your zipped copy
• It would be a good idea to have a team member try to pass the zip file to another member to make sure everything is self-contained and runs properly based on the zip-file alone.  (test your zip file on an empty/fresh cadence 6 installation with no libraries)
  
• Your final design top-level with padframe:
• Must pass DRC check
• Must pass LVS
  
• At final demonstration:
• Show successful simulation of your final design in ADS
•  Show successful simulation of your final design in Cadence ADEXL/spectre. 
  
• Show layout of your circuit passing LVS and DRC including padframe.
  
• On this day, your group must submit final design files for fabrication,
• This device will be fabricated
• At least one team member must commit to do the testing when the chip is received
• MOSIS will terminate UNC Charlotte fabrication privileges, if you do not submit a report of your test results.

• Final report
  
• Final report is due at beginning of final exam period, using final report template, including the plots shown in the design reviews above, updated for the final design,  
• Each team must turn in a report that includes for each assigned circuit:
• Schematics for the assigned circuits from both ADS and Cadence as in the Schematic/simulation design review above
• Schematics for the test circuits for the assigned circuits from both ADS and Cadence as in the Schematic/simulation design review above
• Simulation results from both ADS and Cadence as in the Schematic/simulation design review above
• Layouts for each of the cells for the assigned circuits in Cadence Layout XL as in the layout design review above
• The top-level layout
• The Top-level schematic
• A table showing the pinout, whether each pin is in/out, the needed dc bias voltage for input pins, the expected dc voltage for output pins
  
• Email your final report by 5:00 PM on the day of the scheduled final exam to tpweldon@uncc.edu , no hard-copy required.
  
• Your final report must be self-contained.  In 4 months, you will forget the pinouts, function, and bias levels of your circuits! You will use the report as a guide to refresh your memory and test your circuits after they return from fabrication.
  
• Spring semester: Plan to test your chips!  MOSIS will terminate UNC Charlotte fabrication privileges, if you do not submit a report of your test results.