EEGR6437, Mixed Signal IC Design Project

rev2002b

Overview

ALL PROJECTS MUST BE IN 0.5 MICRON AMI process unless otherwise approved by instructor. If you need to use BJT's in your project, you will have to use AMI 1.2 micron.

The objective of the project is to design a mixed-signal integrated circuit. Each group will have the primary task of completing a particular design. However, all groups are encouraged to work together to ensure successful integrated circuit designs. A list of example projects is below.

As an alternative, students interested in some special project can propose any reasonable mixed-signal design project. See the instructor at once, if this is the case. In general, only exceptional proposals will be considered.

As part of this project, groups are expected to research alternative approaches to the problem. Note that one article/book section is required to be attached to the final report.

Finally, all groups MUST commit to testing their chips when they are received back from the foundry. At least one student in each group must be available in the spring semester to test the chip. This is extremely important, since the university can lose access to the fabrication service if chips are not tested!!!

Poor designs may not be submitted to fab, entirely at the instructor's discretion.

A good start for project ideas is the course textbook.

Group Formation

Organize into groups of two or three and select a project of mutual interest. It is most important to find a group with a project that you have interest in, so use the first week to discuss projects with other members of the class. At least one member from each group must agree to test the chip when it is received during the following semester.

Try to select different projects. At the instructor's discretion, the best proposal for a particular type of project (i.e., analog to digital converter) may be accepted. In this case, other siliar proposals will be rejected, and new propoals will have to be resubmitted.

Problem Resolution

Guidelines (If members of a group are not contributing)

Grading and Schedule

The grade for the final project will be allocated to each task as indicated below.

  • Proposal: 10%

    • Typically due the 8th week of semester. (Oct 21)

    Each group must submit a set of specifications along with a project proposal (see format below). 5 pages maximum, excluding cover page. This is your statement of work.

    You must submit a hardcopy of the proposal and email the proposal as an MSword document to the instructor.

    Your proposal must include:
    (Label your sections exactly as below)

    1. Cover page
      Title of project and group members.
    2. Overview
      1-paragraph overview and project description
      i.e., the proposed project is an 8-bit DAC, with 1 LSB linearity, 40 MHz sample rate, with latched synchronous input, and buffered output to drive 10 pF and 100 ohms, with output voltage range of 1 to 4 volts.
    3. Preliminary block diagram
      give the block diagram, and explain the blocks
    4. Preliminary specification
      You MUST include a table of specs
      You must, in your discussion, describe each of the specs in the table.

      Specs should include, as appropriate, things such as:

      Speed (clock)
      bandwidth (Hz)
      Input/output voltage ranges
      Input signals and pincount (i.e., "data bus in", 8 pins)
      Output signals and pincount
      Output loading in pF and ohms (5 pF minimum! )
      Is the input latched?
      Parallel or serial input?
      What is the total number of pins?
      On-chip counters to help test?
      Can you partition the circuit so that separate power supply pins can power on/off different subcircuits?
      Can you tap and measure intermediate stages or subcircuits?

      For a few examples of specs to include:

    5. For DACs (see chapter 28,29): give sample rate, bits resolution, linearity, buffering, latching, output load (pF and ohms), architecture(R2R, resistor string, charge scaling, etc.)

    6. For ADCs (see chapter 28,29): give sample rate, bits resolution, linearity, buffering, sample/hold, latching, output load (pF and ohms), analog signal bandwidth, architecture (flash, pipeline, integrating, successive approximation,sigma-delta,etc.)

    7. For other devices give similar details, and consult with the instructor on what specs should be included.

    8. Test plan
      You MUST include a block diagram of your test setup
      Your block diagram of your test setup will likely include a signal generator and oscilloscope along with a block diagram of your chip and labeled pins that connect to the oscilloscope and generator.
      You MUST include a timing diagram for input/output signals.
      What are your input/output signals for test?
      How much circuitry will be on-chip to help test?
      When you get the chip, will you have to add external parts to test it?
      What equipment is available in the stockroom/senior lab?
      Can you tap and nmeasure intermediate stages or subcircuits?

  • Preliminary design review : 10%


    • Typically due end of 10th week of semester. (Nov 9)

    You must submit a set of schematics along with accusim simulation, sufficient to show that your design is functional. 10 page maximum, excluding cover page and appendix.

    The design review must include your original proposal in an appendix. You must submit a hardcopy of the design review and email the design review as an MSword document to the instructor.

    Your design review must include:
    (Label your sections exactly as below)

    1. Cover page
      Title of project and group members.
    2. Overview
      as in proposal, but updated for any changes
    3. Block diagram
      as in proposal, but updated for any changes
    4. Specification
      You MUST include a table of specs
      You must, in your discussion, describe each of the specs in the table.
      as in proposal, but updated for any changes
    5. Test plan
      as in proposal, but updated for any changes
    6. Detail schematics
      Include a full set of schematics for your project Make sure you describe the schematic (i.e., M1 - M7 comprise the pre-amplifier, C7 is for compensation, etc.)
      Also, make sure you relate the detail schematic to the bolck diagram.
    7. Simulation Results
      Include sufficient simulation results to prove that your project meets your specifications
      Do not forget to add loading (5 pF minimum) to the outputs!
      Your simulation MUST be using a top-level shematic containing ONLY the top-level symbol of your design plus external components such as 5 pF load, ground, power, etc.
    8. Appendix: original proposal

  • Preliminary layout: 10%

    • Typically due end of 12th week of semester. (Nov 18)

    You must submit a full layout in padframe, sufficient to show that your design will fit in the padframe. 1 pages maximum.

  • Final Report: 50%

    • Typically due at scheduled final exam period.(12:00 Dec 16)

    Final report (see format and guidelines below).

  • Design Files turned in: 10%

    • Typically done on last class meeting of semester. (Dec 7)

    Design files must be copied (using DMGR) to the instructor's directory. The files must be contained in a single appropriately named directory (i.e., myname_dac8bit_fall02).

  • Final demonstration and tape-out: 10%

    • Typically done on last class meeting of semester. (Dec 7)

    You must demonstrate your final design and full layout in padframe.

    You must pass :

  • LVS
  • DRC

    • and you must demonstrate this to the instructor. You will also demonstrate your schematics and simulation.

  • MOSIS Submission:

    Your design must be complete, free from obvious errors, and must be submitted to MOSIS for fabrication without any errors. MOSIS runs automatic checks for fill patterns, so you MUST use filler to meet minimum density requirements. You must pass LVS and DRC at top level, and you will demonstrate this to the instructor. If you do not meet all of these requirements, 30 percent will be deducted from your total final project grade.

  • Make-up :

    You may, at the discretion of the instructor, fix any errors or problems and be given the opportunity to re-demonstrate and re-submit your MOSIS design during the final examination period. Typically done during the final examination period.

    • Final Report

    The final report must include your original proposal and design review in two appendices. You must submit a hardcopy of the final report and email the proposal as an MSword document to the instructor.

  • Final report for each group due on date indicated above
  • Format: 25 Page Max. typewritten body of report, excluding coverpage

    Your design review must include:
    (Label your sections exactly as below)

    1. Cover page
      Title of project and group members.
    2. Overview
      as in proposal, but updated for any changes
    3. Block diagram
      as in proposal, but updated for any changes
    4. Specification
      You MUST include a table of specs
      You must, in your discussion, describe each of the specs in the table.
      as in proposal, but updated for any changes
    5. Test plan
      as in proposal, but updated for any changes
    6. Detail schematics
      Include a full set of schematics for your project
      Make sure you describe the schematic (i.e., M1 - M7 comprise the pre-amplifier, C7 is for compensation, etc.)
      Also, make sure you relate the detail schematic to the bolck diagram.
    7. Simulation Results
      Include sufficient simulation results to prove that your project meets your specifications
      Do not forget to add loading (5 pF)to the outputs!
      Your simulation MUST be using a top-level shematic containing ONLY the top-level symbol of your design plus external components such as 5 pF load, ground, power, etc.
    8. Comparison of specs to simulation results
      You MUST include a table comparing specs to simulation results
      Make sure the simulation results are given in the previous section.
    9. Final layout
      Top-level printout, includes padframe
    10. LVS printout (smiley face)
      Printout of the LVS result
    11. IC pin out
      !! you must label all pins on a layout.
      To do this print out your top-level layout including padframe, and label all the pins with the same names as your schematic port names
      Dont forget power pin and ground!!
    12. Conclusion

  • LABEL all sections EXACTLY as above, IN ORDER GIVEN ABOVE
  • Must include copy of 1 book/article on topic
  • Article must be relevant to your design
  • Must include mentor:
    Schematic (Label critical voltages and critical currents)
    Simulation plots
    IC layout (in padframe)
    IC layout WITH PINS LABELED!!
  • Simulation data must be sufficient to verify design
  • Meet all specs

    • Alternative Project Ideas

  • See ADC and DAC ideas in chapters 28, 29.
  • See sigma-delta converter in chapter 29.
  • See other sections of text (but beware of switched cap designs)

  • Single-chip AM/FM/CitizenBand Radio

  • 10 microvolts input
  • 1 volt output
  • 500 ohm input and output
  • Tunable over full band
  • AGC Amplifier
  • 30 dB adjacent channel selectivity
  • 2-bit digital input for gain adjustment
    00=40 dB, 01=30 dB, 10=20 dB, 11=10 dB

  • Single-chip QAM Modulator

  • 2x8-bit DAC inputs, 20 MS/s
  • 1 volt output
  • on-board oscillator (100 - 200 MHz)
  • 500 ohm input and output
  • Tunable over full band
  • On-Board gilbert cells
  • On-board phase quadrature LO

  • A/D Converter

  • 8 Bit
  • Parallel interface (parallel output data port plus clock port)
  • input voltage range = full supply (0 - 5 V)
  • 25 Megasamples/second
  • Includes sample and hold circuit
  • S/H Accuracy +/- 0.5 % of full-scale

  • Phase-Locked Loop

  • Phase/Frequency Detector
  • 1 MHz phase detector inputs
  • Divide by 64 synchronous prescalers for reference and VCO
  • Adjustable prescalers

    • Copyright information