Introduction to Mentor Graphics

 
Rev. 20Aug04
Tom Weldon
© 1997-2004

Preface
This paper provides an introduction to the use of the Mentor Graphics software package. Components of the Mentor Graphics package that are covered in this paper include Design Manager, Design Architect, IC Graph, Quicksim, Accusim, and Design Viewpoint Editor. The reader is quickly taken through the fundamental steps of schematic entry, simulation, and IC layout.
The content is targeted to the MOSIS IC fabrication service ( http://www.mosis.org ). Thus, some of the examples presume that the MOSIS ASIC Design Kit (ADK) is installed. This suite of tools is targeted to the MOSIS service and is available by ftp from Mentor Graphics. Directions for obtaining the kit are posted on the Mentor Graphics website http://www.mentorg.com .
The MOSIS kit does not contain some local customizations that may be referred to in this and other documents. These local customizations have been added to support a more complete Schematic Driven layout (SDL) package.
In the years since this tutorial was first prepared, Mentor Graphics software has undergone many upgrades. Depending on the particular software revision, some of the tools may appear different, and you may need to adapt some of the instructions to your particular installation. In most cases, it should be fairly straightforward to interpret how the instructions should be adapted.
The particular MOSIS processes we are using are the AMI 1.5 micron process and the AMI 0.5 micron process. The 1.5 micron process is "squeezed" down to 1.2 microns (for historical reasons). The 0.5 micron process is a CMOS process, while the 1.5 micron BiCMOS process includes BJT's.
In the class, we will do some preliminary projects using BJT's in the 1.5 micron process. Later, we will switch to the 0.5 micron process. In most cases (unless you need BJT's), your final project will be in the CMOS AMI 0.5 micron process.
The tools at our university are based on a slightly expanded version of the Mentor Graphics ADK (ASIC Design Kit). The official ADK website is http://www.mentorg.com/partners/hep/index.html , and you can find the ADK user manual on our file system at /afs/uncc.edu/coe/unix/opt/mgc/mosis/ADK20_user_guide.pdf ( note that our setup is a modified version of ADK20_user_guide.pdf, but the ADK20 guide may give more up-to-date instructions)
Mentor Graphics, Mentor, IC Station, ICgraph, ICtrace, ICverify, QuickSim, Calibre, AccuSim, Analog Station, Design Architect, are trademarks of Mentor Graphics Corp, along with many other trademarks listed on http://www.mentor.com/utilities/trademarks.html .

Contents

1  Preliminaries
    1.1  Login File and Environment Variables
    1.2  Brief Summary of Some UNIX Commands
    1.3  Mentor On-Line Help
2  Design Manager: Basic Project Management
    2.1  Starting Design Manager
    2.2  Setting the Working Directory
    2.3  Basic Navigating
3  Design Architect: Basic Schematic Entry
    3.1  Schematic Entry for a CMOS Inverter
        3.1.1  Accessing the MOSIS ADK Library
        3.1.2  Placing Parts on the Schematic
        3.1.3  Wiring the Parts on the Schematic
        3.1.4  Renaming I/O Ports
        3.1.5  Checking and Saving the Schematic
    3.2  Printing Schematics
    3.3  Strokes: Mouse-Based Commands
    3.4  Symbol Creation
4  Quicksim II: Logic Simulator
    4.1  Preparing for Quicksim Using adkdve05 and adkdve12
    4.2  Simulating the Inverter Schematic with Quicksim
    4.3  Design Viewpoint Editor
        4.3.1  Using Design Viewpoint Editor
        4.3.2  Creating a Quicksim Design Viewpoint from Scratch
5  Accusim: Analog (SPICE) Simulator
    5.1  Preparing for Accusim with adkdve05 or adkdve12
    5.2  Simulating the Inverter Schematic with Accusim
    5.3  Measuring Currents
    5.4  AC Analysis
    5.5  DC Sweep Analysis (Transfer Function)
    5.6  DC Operating Point
    5.7  Preparing for Accusim Using Design Viewpoint Editor
        5.7.1  Preparing a Design Viewpoint From Scratch
6  IC Station: Schematic Driven IC Layout
    6.1  IC Station: Schematic Driven Layout (SDL) for AMI 1.2 Process
        6.1.1  Preparing for IC Layout Using adkdve12
        6.1.2  Schematic Driven IC Layout
    6.2  IC Station: Schematic Driven Layout (SDL) for AMI 0.5 Process
        6.2.1  Creating an AMI05 design
        6.2.2  Plan Ahead: Overview of File Heirarchy
        6.2.3  Creating the "Main Schematic"
        6.2.4  Creating the "Main Layout"
        6.2.5  Creating the "Top Schematic"
        6.2.6  Creating the "Top Layout"
7  Digital SDL Design Using Standard Libraries
    7.1  Schematic Entry for Digital Circuits
        7.1.1  Accessing the MOSIS SDL Library
        7.1.2  Placing Parts on the Schematic
    7.2  SDL IC Layout for Digital Circuits
    7.3  IC Station: Digital Schematic Driven Layout
        7.3.1  Preparing for IC Layout Using sdl_prep
        7.3.2  Digital Simulation
        7.3.3  Digital Schematic-Driven IC Layout
        7.3.4  Autorouter
8  IC Pads and Padframes
        8.0.5  Padframe Generation
        8.0.6  Changing Digital Pads to Analog Pads
        8.0.7  Padframe Problems
9  Fabrication, GDS-II, and Tape-Out
Index

Chapter 1
Preliminaries

The Mentor Graphics software package consists of a large number of executable files, documents, libraries, and other components. The locations of these files vary from system to system, so it is necessary to incorporate some mechanism for handling the differences that naturally occur between the installations at different sites. Many of these details are handled using start-up scripts and environment variables.
Although these startup scripts simplify the use of the software for the end user, it may be necessary for the user to do some minor editing of start-up files before the software can be used. The following sections go over some of the tasks that the user may need to perform before using the Mentor Graphics software. The user should check with their system administrator before undertaking the following changes.

1.1  Login File and Environment Variables

Before using the Mentor Graphics software, certain environment variables must be initialized to indicate the location of various directories on the system. To simplify this process, it is only necessary to add the following lines to your ".cshrc.sol9" file. Files that begin with a "dot" are hidden in unix, and the "ls -a" command must be used to list hidden files. Open a command tool shell and type"nedit .cshrc.sol9" in your home directory to edit the file. Contact the system administrator for the location of Mentor for your system). At our university, see also http://www.coe.uncc.edu/~tpweldon/mentoradk/ .

 

alias ic05 '/afs/uncc.edu/coe/unix/opt/mgc/mosis/tpwadk17/startups/tpwicami05'
alias dmgr05 '/afs/uncc.edu/coe/unix/opt/mgc/mosis/tpwadk17/startups/tpwdmgrami05'
alias ic12 '/afs/uncc.edu/coe/unix/opt/mgc/mosis/tpwadk17/startups/tpwicami12'
alias dmgr12 '/afs/uncc.edu/coe/unix/opt/mgc/mosis/tpwadk17/startups/tpwdmgrami12'
alias adkdve05 '/afs/uncc.edu/coe/unix/opt/mgc/mosis/tpwadk17/startups/tpwadk_dveami05 \*' alias adkdve12 '/afs/uncc.edu/coe/unix/opt/mgc/mosis/tpwadk17/startups/tpwadk_dveami12 \!*'

 
 
After editing the file, check for errors by executing the command "source .login.sol9" and fixing any errors.
After successfully sourcing the file, type the command "alias" to see that your aliases have been added.
Hereafter, if you want to run ICStation for AMI 0.5 micron process, type the corresponding aliased command "ic05" as defined in your cshrc file. Similarly, type "dmgr12" to run Design Manager (dmgr) for the AMI 1.2 micron process. Note that you should run Design Architect and Accusim from within Design Manager, because this will cause Design Manager to pass the setup (variables, paths, etc.) on to the child processes. However, YOU MUST RUN ICstation using the aliased commands ic05 or ic12. You cannot run ICStation from within the same dmgr as used to run design architect and accusim (for some unexplained reason). To run the latest versions of IC Station, use the aliased commands ic05 or ic12 corresponding to AMI 0.5 micron or 1.2/1.5 micron process.
The PATH environment variable is sometimes overwritten by improperly written initialization files. (Type "echo $PATH" if you want to see how your path is set.) This problem is usually caused by the "set path =" or "setenv PATH"statement of the ".cshrc.solx" or ".login.solx" file. This path can be improperly set, and may not incorporate the existing path that was originally established. Since the .login file runs after the .cshrc file, it can improperly override the path. Other startup files for the windowing system can cause similar side-effects. In these situations, a variety of error messages can occur.
The use of the above aliases should prevent such problems with the PATH variable. In these. the PATH is not set until the aliased commands are run. It is possible, however, that initialization of your PATH at login may cause problems (i.e., PATH too long).
If you do not already have a directory named "mentorg" in your home directory, create one by entering "cd" at the command prompt in a command tool window. After this, enter the command "mkdir mentorg." This new directory will contain all of the Mentor designs.
Note: ".login" is only executed when you first log into the system. If you find that you must make changes to your ".login" file, you must log out, and log back in, before any changes take effect. (Actually, you may need to log out and log in twice, because of the way some startup scripts works.)

1.2  Brief Summary of Some UNIX Commands

You will need to become familiar with a few UNIX commands. These commands must be entered in a command tool window or other terminal window. Whenever you need to find help on UNIX command "yyy", type "man yyy" or "apropos yyy" to get on-line information. (Most sytem administrators do not install apropos correctly, so apropos may not work.) The answerbook utility or other system help tools can also be used on Sun workstations to access help on commands. A few of the most common commands are listed below.
Open a terminal window and type the command "ls" to list the directory you are currently in. Type the command "ls -alF" to list the directory you created, except with more information. Type the command "man ls" to explain the options. Add the line "alias ls \'ls -F\' " to your .cshrc.sol9 file if you prefer this.
Other general help topics are found at http://www.coe.uncc.edu/mosaic/ and more unix help is found at http://www.coe.uncc.edu/~tpweldon/courses/eegr6118/cplus.html and http://www.coe.uncc.edu/mosaic/mosaic_help/unix_help/os/ .
The mouse behavior follows conventions similar to other software. In most cases, a single click of the left mouse button is used to select items, activate buttons, etc., and a double click is used to launch applications. The right mouse button is pressed and held down to bring up hidden pop-up menus within panes. The left or right button is used to drag down pull-down menus from the menu bars at the top of windows.
Window behavior is also similar to that of other applications. Currently selected windows are highlighted, or change color, to indicate that they are the active panes or windows. In the Mentor tools, the menu bar at the top of the main window can change content depending on the currently selected pane (or frame) within the window. Similarly, the action of function keys can change depending on the currently selected pane. Note that the action of function keys are sometimes listed at the bottom of the window, but YOU CANNOT CLICK on the area at the bottom - you must use the function key. For each key, up to 4 rows of functions may be listed. The top row corresponds to the key alone, second row is the shifted key, third row is Control+key, and the fourth row is Alt+key. You may also use your mouse to click the function-key area at the bottom of the window.
Error messages are typically displayed at the bottom of windows, and can be scrolled up or down (only one line appears at a time). Pay careful attention to the error messages at the bottom of the window, particularly when checking schematics, layouts, etc. Ignoring an error can result in hours of wasted time!
Various tools in Mentor Graphics require a significant number of colors. To avoid problems, exit all applications except for commandtool before running any Mentor software. Aplications such as web-browsers and image viewers seem to cause particular problems with Mentor. Also, remove any "fancy" colors and backgrounds from your desktop setup.

1.3  Mentor On-Line Help

The menu bar for each of the Mentor tools includes a "Help" pull-down menu. The "Open Bookcase" option accesses on-line manuals. In some instances, an "Open Tutorial" option is also available. When the manuals are requested, the BoldBrowser software tool displays the on-line manual at the terminal. The magnification can be adjusted so that each page fits the screen. Other functions include search capabilities and a mechanism for printing 4 pages of manual on a single printed page. Please refrain from printing manuals; they are hundreds of pages long, and the on-line versions are more convenient and searchable.

Chapter 2
Design Manager: Basic Project Management

The Mentor Design Manager is the main user interface both for accessing other Mentor software tools and for maintaining the directories and files that comprise designs. Wherever possible, Design Manager should be used to run all of the other software tools (Design Architect, IC Graph, Accusim, etc.) to ensure that environment variables are properly set and passed to each program. In addition, Design Manager MUST be used to move and copy files that are part of a design. NEVER use UNIX commands (cp, rm, etc.) to move and copy Mentor files. The Mentor software associates special numerical codes with the files it creates to keep track of design files, revisions, etc. If Design Manager is not used to move or copy design files, the numerical codes associated with the files will not be properly updated, and errors will occur when accessing the design later. If you move or copy files without using Design Manager, you WILL lose all of your work!
Various tools in Mentor Graphics require a significant number of colors. To avoid problems, exit all applications except for commandtool before running any Mentor software. Aplications such as web-browsers and image viewers seem to cause particular problems with Mentor. Also, remove any "fancy" colors and backgrounds from your desktop setup.

2.1  Starting Design Manager

To run design manager, type the command "dmgr05" in a command tool window. (If you want to run the AMI 1.2 micron process, type "dmgr12" instead.) You should then see the following output in your terminal window as the program begins to run:

 
 
 
Starting Mentor Graphics ...
Design Manager v8.10_1.3 Mon Nov 3 15:46:13 GMT 2003
... etc., etc.
Make sure that there are no error messages in this terminal window. Double check this terminal window even after the Design Manager window below appears!
In a few seconds the Design Manager window should appear as in Fig. 2.1.
./ps/dmgr2.gif
Figure 2.1: Design Manager window. The left pane is the Tools pane containing icons that are used to launch the Mentor software tools such as Accusim and Design Architect. The center pane is the Navigate pane and shows the design files that exist in the directory. This directory should be the mentorg directory that you created earlier. The rightmost pane is the Palette. Additional Tools and Navigate panes can be launched by clicking on the corresponding icons in the Palette.

2.2  Setting the Working Directory

Before proceeding, first check that the working directory in use by Design Manager is correctly set to "~/mentorg/intro," where "~" is a shell macro that represents your home directory. To do this, click and hold down the left mouse button on the MGC drop-down menu at the top of the Design Manager window, then pull down the menu selection MGC->LocationMap->SetWorkingDirectory, then release the button. The drop-down menu is shown in Fig. 2.2.
./ps/dmgr_setdir.gif
Figure 2.2: Design Manager window. The command denoted by "MGC-> LocationMap-> SetWorkingDirectory" is shown above. The selection is made by clicking and holding the the left mouse button and dragging down the selection.
First, create a new directory "~/mentorg/intro" by first changing to directory ~/mentorg using the Navigator pane. Make sure the Navigator pane is highlited in the Design Manager window, since the highlited pane affects the items that appear on the top menu bar. Add the new directory "intro" by using the pull-down menu command Add->Directory.
Note: Design Manager is the best way to work with files and folders, as in the example of creating the intro directory. Try to NOT use UNIX commands when working in the ~/mentorg directory or any subdirectory. This is because Mentor often creates hidden auxiliary files that affect the interpretation of the files created. It is impossible for you to know how to handle these auxiliary files. At some point, you may notice these files in the directories. Do not move, delete, or tamper with any of these files. NEVER use UNIX commands (cp, rm, etc.) to move and copy Mentor files. The Mentor software associates special numerical codes with the files it creates to keep track of design files, revisions, etc. If Design Manager is not used to move or copy design files, the numerical codes associated with the files will not be properly updated, and errors will occur when accessing the design later.

2.3  Basic Navigating

After creating the "intro" directory, double-click on the "intro" folder in the Navigator pane to enter the ~/mentorg/intro directory. To return to the parent directory, click on the "up-arrow" at the bottom of the Navigator pane.

Chapter 3
Design Architect: Basic Schematic Entry

Design Architect is the Mentor tool for entering circuit schematics. In the following, a new schematic for a CMOS inverter is created. The ADK Library is used to implement the inverter using MOS devices from the ADK library for the MOSIS chip fab facility.
In the Tools pane of Design Manager, double-click on the Design Architect icon shown in Fig. 3.1. This will launch the Design Architect application. An informational terminal window is also launched; this window should be iconified. Make sure that there are no error messages in this terminal window.
./ps/da_icon.gif
Figure 3.1: Design Architect icon.

3.1  Schematic Entry for a CMOS Inverter

When the Design Architect window first opens, make sure that there are no error messages in the message area at the bottom of the window. Make a habit of checking the message areas whenever you open any Mentor Graphics tools, and after every action/command/operation while using the tools. This habit may save many hours of work.
At the menu bar in Design Architect, check that the working directory is "~/mentorg/intro" by using the pull-down menu command MGC->LocationMap->SetWorkingDirectory.
Open a new schematic by using the pull-down menu command File->Open->Sheet, and entering the file name "inv1" at the end of the directory path (dont forget the "/" before typing "inv1"). Click the "Editable" button on the OpenSheet pop-up window if it is not already selected. An empty pane (design sheet) will appear in the Design Architect window.

3.1.1  Accessing the MOSIS ADK Library

The design will be implemented using devices from the ADK (ASIC Design Kit) library. Select the ADK libraries by using the pull-down menu command Libraries->ADKLibrary. If the ADK library option does not appear as shown in Fig. 3.2, there is something wrong with your environment, your .cshrc aliases, or with the installation of ADK.
./ps/da_mdkit.gif
Figure 3.2: Design Architect window. The command denoted by "Libraries->ADKLibrary" is shown above.
The Palette in the Design Architect window should now be the ADK Library Palette as shown in Fig. 3.3. Click on "SDL Parts" item in the palette. The SDL (schematic driven layout) parts should appear in the Palette .
./ps/da_sdlparts.gif
Figure 3.3: Design Architect palette for Mosis Design Kit SDL parts.

3.1.2  Placing Parts on the Schematic

The first step is to place the devices in the Schematic Pane for the inverter circuit of Fig. 3.4. Click on "gnd" (or click "vss" in older versions of the ADK) in the Palette, and the symbol for gnd appears in the small pane above the Palette. Move the mouse pointer into the schematic sheet pane (without any mouse-buttons being depressed), and the symbol will appear on the schematic. Drop the symbol in position by clicking the left mouse button. Position the remaining devices on the schematic as in Fig. 3.4 using the n-fet-4, p-fet-4, and vdd devices. Leave some room between all of the devices, since the connections will be added next. Also add a "portin" and "portout" to the schematic for the inverter input and output. You may need to use your "page down" key scroll down to hidden items in the palette, or use thr right-mouse-button to select scroll bars in the palette. You may need to zoom out (View->ZoomOut->2) on the schematic or use the scroll bars to give enough room to complete the schematic.
Note: it may be necessary to use "gnd" instead of "vss" for circuits that use older versions of the MOSIS Design Kit standard cells elsewhere in the circuit. This is because the standard cells use the "gnd" connection.
Note: Placement of the devices on the schematic is important. Automatic placement software that is used to produce a layout attempts to keep the devices in the same relative position as on the schematic.
./ps/da_schem.gif
Figure 3.4: Design Architect Schematic Pane.

3.1.3  Wiring the Parts on the Schematic

Next, use the right mouse button to bring up the pop-up display menu in the Palette pane. Select the "Display Schematic Palette" option by dragging the mouse down the menu as shown in Fig. 3.5(a). The Display Schematic Palette then appears as shown in Fig. 3.5(b). Click on the "Add/Route" icon, then the "Add Wire" icon, in the Palette to begin adding wires.
 

./ps/da_dispsch.gif ./ps/da_dispschpal.gif
 


 
(a) (b)
 

Figure 3.5: Design Architect. (a) Palette pop-up menu. (b) Schematic Palette.
Note the diamonds that mark the proper placement of the connection on each device. To add each wire, first click the left mouse button on one of the device terminals. Then, move the mouse to the terminal of the second device and double-click to complete the connection. Note that right angle bends can be added to a connection by just clicking the left mouse button at any point along the path between the endpoints of the connection. Also note the pop-up window (prompt bar) at the bottom of the screen shown in Fig. 3.6. Click on the cancel button in this pop-up when finished wiring the schematic. As you wire the circuit, you can use right mouse button to bring up editing functions in the pop-up menu of the Schematic Pane to undo, delete, paste, etc.
./ps/da_wirepop.gif
Figure 3.6: Design Architect: Add Wire pop-up.
As the connections are being made, the wiring appears as a dashed line. This indicates that all of the dashed connections are "selected," just as if the schematic sheet had been opened and each connection was clicked on with the mouse in order to perform some operation on the connections. At the bottom of the Design Architect window, the function key bindings are listed. Use the "F2" key to unselect all of the wiring. After this, the dashed lines should become solid.

3.1.4  Renaming I/O Ports

After unselecting all of the schematic, the status line right below the Design Architect menu bar should indicate that no items are selected with the message "Sel: 0+." Select the input port by clicking on it with the left mouse button; the message should become "Sel: 1+."
With the input port selected, use the right mouse button to bring up the pop-up menu in the Schematic Pane to execute the Properties->ChangeTextValues command. In the dialog box, enter "IN1" for the text. As you do this, a second text area appears where "OUT1" is to be entered. Dont type the enter key, use the mouse to move to the second text area. Click "OK", and the pop-up disappears with a new pop-up appearing called SEL AR. Click on the "NET" text field at the input port, and the text should be replaced by "IN1." Click on the "NET" text field at the output port, and the text should be replaced by "OUT1."

3.1.5  Checking and Saving the Schematic

Check the schematic sheet using the command Check->Sheet->WithDefaults from the menu bar in Design Architect. There should be no errors or warnings. Close the check window, and reselect the Schematic sheet pane.
If you have opened several schematic panes during your session (even if you have since closed the panes), sometimes Design Architect will give warnings even though the schematic is correct. In these strange cases, exit Design Architect and restart it, and then only open the schematic you were checking. In most cases, the schematic will pass without errors/warnings when it is the only schematic opened during your session.
Finally, save the schematic by first selecting the Schematic sheet pane, then using the pull-down menu-bar command File->SaveSheet->DefaultRegistration.

3.2  Printing Schematics

To print schematics directly to a printer from within Design Architect you must first set up the printer, then print the schematic.
  1. From the menu bar: MGC->Setup->Printer
  2. Select the printer name if there is a list given, otherwise enter the printer name
  3. Click OK, and the pop-up will close
  4. Select the pane of the schematic you want to print
  5. From the menu bar: File->PrintSheet
  6. OK
To print schematics from within Design Architect by saving to a file:
  1. Print file from mentor (File->ExportGraphics)
  2. Select EPS
  3. click on select format button
  4. Enter the desired output filename
  5. OK
To view schematics with Ghostview, open a terminal window and navigate to the directory where you saved the schematic and type "gv myfile.eps"
To convert to a gif format, type "ps2gif myfile.eps myfile.gif"
( Plot/print the schematic of your inverter as plot P1 )

3.3  Strokes: Mouse-Based Commands

Mouse-based commands can execute many of the commands typically done by keystrokes, function keys, Palette icons, and drop-down menus. These mouse-based commands are referred to as "strokes." A stroke consists of depressing the center mouse button in the Schematic Pane and tracing out some pattern (stroke) on the screen. As the stroke is being performed, it appears in red on the screen.
To see the action of these stroke commands, create a stroke in the pattern of a question mark on the screen, as shown in Fig. 3.7. A help window should appear that contains a summary of stroke commands including the excerpt shown in Fig. 3.8. Note in particular the "view area," "view all," and "unselect" strokes.
Note: different applications use different definitions for strokes. Thus, a particular stroke pattern may have different effects in different applications such as IC Station, Design Architect, etc.
./ps/da_quest.gif
Figure 3.7: Question mark (help) stroke.
./ps/da_strokes.gif
Figure 3.8: Partial list of Design Architect strokes.

3.4  Symbol Creation

The inverter schematic can be assigned a symbol, so that the circuit may be reused as part of some larger design project. This approach simplifies hierachical designs.
With the schematic loaded, use the Design Architect pull-down menu-bar command Miscellaneous->GenerateSymbol to begin creating the symbol. In the dialog box, keep the default options and click OK. (If a symbol already exists for this schematic, also choose the "Replace Existing" option.) The Symbol Editor pane should appear on screen with the two ports named as in the schematic (IN1, OUT1).
To give the symbol a name, first select the symbol by clicking on the rectangular box outlining the symbol. The box should change from solid to dashed. Click on the "TEXT" icon, then the "ADD TEXT" icon in the Palette. Enter "INV1" in the pop-up text window, then click on the crosshair in the pop-up window, then position the cursor where the text should be located, and finally click the left mouse button to position the text. Press the F2 function button to deselect all elements.
To change the rectangle to a triangle, select the rectangle. Use the right mouse button to access the pop-up menu and select Delete->Selected. Use the pull-down menu command View->Zoom->2 to zoom the symbol. Select the output pin (both the line and diamond) and use the pop-up menu to Move->Selected. Click on the "Draw" icon in the pallet, then click the "Add Polygon" icon, and add a triangular polygon. Click on "Add Circle to add a circle. The final symbol should resemble Fig. 3.9.
Check the symbol using the menu-bar command Check->WithDefaults. (Ignore two warnings "The following pins on symbol are not on interface.") Save the symbol with the command File->SaveSymbol->WithDefaultRegistration, then close the Symbol pane.
./ps/da_invsym2.gif
Figure 3.9: Design Architect: new symbol after editing.
( Plot/print the schematic of your inverter as plot P2 )

Chapter 4
Quicksim II: Logic Simulator

Quicksim II is the Mentor software tool that performs digital logic simulations. For analog simulations, refer to Accusim in Chapter 5.

4.1  Preparing for Quicksim Using adkdve05 and adkdve12

Before proceeding, the design files must be prepared for simulation. However, the procedure is fairly complicated. To simplify matters, the command "adkdve05" (or "adkdve12") automatically runs Design Viewpoint Editor and prepares the file for simulation with Quicksim. For reference, a short overview of how this would be done manually using Design Viewpoint Editor is later provided.
The preferred method for preparing the schematic for simulation in Quicksim is provided as part of the ADK design kit for MOSIS. To use this method, execute the command "adkdve05 ." in the directory containing the design ( ~/mentorg/intro/inv1). The "." is necessary, and indicates that the current directory is the directory containing your design. For the inverter design example, change to the inverter directory, and run adkdve05 as follows:

 
 
cd ~/intro/inv1
adkdve05 .
After the script finishes running, a new directory "~/mentorg/intro/inv1/sdl" should be created along with several new files including "ami05.dvpt_1," and "ami05.Eddm_design_viewpoint.attr." These auxiliary files are hidden in Design manager, but can be seen using the UNIX "ls" command in a terminal window. These files represent the newly created design viewpoint for Quicksim II that was given the default name "ami05" when you ran the command adkdve05.
WARNING! If you are running the CDE window manager, it appears that the PATH environment variable is sometimes overwritten by CDE. Actually the problem is in the "set path =" statement of your ".cshrc." This path is improperly set, and does not incorporate the path as set by .login. In this case, you may get the error message "dsim_prep: file not found." If your PATH variable does not contain any "mentorg" directories, see the comment in Section 1.1.)

4.2  Simulating the Inverter Schematic with Quicksim

In the Navigator pane of Design Manager, navigate to ~mentorg/intro/inv1 directory. In the directory, you should see the design viewpoint "~/mentorg/intro/inv1/ami05" that was created with the command "adkdve05." This design viewpoint file should be located under the mentorg/intro/inv1 directory and appears as a file-folder with the letters "dvpt" indicating design viewpoint. After selecting the file, right-click on the "ami05" icon to pop-up the menu and launch the Quicksim application. In Quicksim, click on the "open sheet" icon in the Palette, or use the menu-bar command File->OpenSheet to see the schematic. The Quicksim window is shown in Fig. 4.1. An informational terminal window is also launched and should be iconified. Use the menu-bar command MGC->LocationMap->SetWorkingDirectory to set the working directory to the design directory ~ /mentorg/intro.
As a different way to start Quicksim, in the Tools pane of Design Manager double-click on the "QuicksimII" icon to launch the Quicksim application. In the dialog box, use the navigator to select the design viewpoint "~/mentorg/intro/inv1/ami05" that was created with the cshell script "dsim_prep." The design viewpoint file should be located under the mentorg/intro/inv1 directory. This file appears as a file-folder with the letters "dv" indicating design viewpoint. After selecting the file, let the remaining dialog box fields be blank with unit timing mode, hidden unit detail, and 0.1 ns resolution. The Quicksim window is shown in Fig. 4.1. An informational terminal window is also launched and should be iconified. Use the menu-bar command MGC->LocationMap->SetWorkingDirectory to set the working directory to the design directory ~ /mentorg/intro/inv1.
./ps/qs_win.gif
Figure 4.1: Quicksim window.
In the Quicksim window, click on the "Open Sheet" icon in the Palette, and the schematic of the inverter should appear. In Quicksim, the schematic is used to select ports for the application of input signals and for the measurement of output signals. The selection of points in the schematic affects actions in other Quicksim panes.
To apply an input signal, click on the input port. All of the wiring connected to the port should appear as dashed lines, indicating that they are selected. Use the F2 function key to deselect if needed. Next, click the stimulus icon in the Palette, then click the "Add Force" icon to add an input signal. In the dialog box that appears, the signal name "/IN1" should appear. Type a 0 in the value field, then tab over to the time field to enter another 0. A second field appears, and type another tab character to go to the second line. Continue entering the data pairs (1,25) and (0,50) as shown in Fig. 4.2. Use the tab character to enter data, because carriage return causes the window to close. Enter OK when you are finished.
./ps/qs_tim.gif
Figure 4.2: Quicksim input force dialog box.
Unselect the input using the F2 function key or the "U" stroke. To select the signals to be observed during the simulation, select the input port and output port in the Schematic Pane, then click on the "Trace" icon in the Palette. A trace pane will be opened, showing the /IN1 and /OUT1 signals labeled on the axis.
To add traces to an existing trace window, you would highlight the traces you want to add and use the command Add->Trace. To delete traces in an existing trace window, you would highlight the traces you want to delete and use the right-mouse-button to DeleteSelected.
To run the simulation, use the menu-bar pull-down command Run->Simulation->ForTime and enter 100 in the pop-up window. Alternatively, click on the Palette "Run." The simulation will run for 100 nS, and the result should look like Fig. 4.3. Use Palette "Reset" ( select state and do not save waveform results) to reset the simulation.
./ps/qs_res.gif
Figure 4.3: Quicksim simulation results.
In the trace pane, use RightClick->Cursor->Add to add the cursor.
The long dashing used in the blue dashed output trace may be hard to read. You can change this to short dashing using MenuBar->Setup->WindowAttributes->CurveStyle for the 12-state 1r, Xr, and 0r signals. (Note: quicksim thinks that your output is resistive, or not strongly driven, because you are using very small FETs.)
Use the right-mouse-button to pop-up the "View->Area" command on the Traces pane to zoom in on the first 100 nanoseconds of the simulation.
( Plot/print the Quicksim simulation trace of your inverter as plot P2 )

4.3  Design Viewpoint Editor

4.3.1   Using Design Viewpoint Editor

You can use Design Viewpoint Editor (DVE) to view the contents of a design viewpoint. Although you are not likely to ever edit a design viewpoint, it is useful to see what is contained in a design viewpoint.
In the Navigator pane of Design Manager, navigate to ~mentorg/intro/inv1 directory. In the directory, you should see the design viewpoint "~/mentorg/intro/inv1/ami05" that was created with the command "adkdve05." This design viewpoint file should be located under the mentorg/intro/inv1 directory and appears as a file-folder with the letters "dvpt" indicating design viewpoint. After selecting the file, right-click on the "ami05" icon to pop-up the menu and launch the DVE application. The final design viewpoint configuration created by the "adkdve05" script is shown in Fig. 4.4.
./ps/dve_dsim.gif
Figure 4.4: Design Viewpoint configuration for Quicksim.

4.3.2   Creating a Quicksim Design Viewpoint from Scratch

Note: You should never need to create a design viewpoint from scratch!
Most users can safely ignore this section. The preferred method for preparing a design viewpoint for simulation is to use the command "adkdve05." See Section 4.1 for details. The following description of Design Viewpoint Editior is for reference only.
If you needed to create the design viewpoint from scratch (instead of using the command adkdve05), you would first start Design Viewpoint Editor, in the Tools pane of Design Manager, by double-clicking on the "DVE" Design Viewpoint Editor icon. This will launch the Design Viewpoint Editor application shown in Fig. 4.5. An informational terminal window is also launched; this window should be iconified. Click on the "Open VPT" icon in the Palette, and use the navigator to select the inverter component. The DVE window may need to be enlarged to see the navigator button in the dialog box that appears. In the navigator, the inverter (inv1) appears as the file-folder icon with the letter "C" inside as shown in Fig. 4.6. In the dialog box, name the viewpoint "ami05" replacing the default name, and click "OK."
./ps/dve_win.gif
Figure 4.5: Design Viewpoint Editor window.
Click on the "Open VPT" icon in the Palette, and use the navigator to select the inverter component. The DVE window may need to be enlarged to see the navigator button in the dialog box that appears. In the navigator, the inverter (inv1) appears as the file-folder icon with the letter "C" inside as shown in Fig. 4.6. In the dialog box, name the viewpoint "qsim," replacing the default name, and click "OK."
Next, select the standard Quicksim setup using the menu-bar command
Setup->QuicksimFaultPathGrade.
The viewpoint is next customized to indicate that the model property "technology" is a primitive (lowest level in the design). From the menu bar, use Edit->Add->Primitive. In the dialog box, enter "model" for the property name, "technology" for value, "Except Flag" off, and a property type of expression.
To give the technology a value, use Edit->Add->Parameter, or click on the same icon in the Palette. In the dialog box, enter "technology" for the name, a property type of string, and enter "ami05" for in the value field. This selects the MOSIS AMI 0.5 micron process. The resulting configuration is shown in Fig. 4.4.
Note that the MOSIS technology parameter was defined at the Quicksim design viewpoint level rather than the schematic level. This allows the schematic to be used for different processes.
The setup process for design viewpoint can become rather complicated. There are other parameters set besides the two mentioned above. To see these parameters, inspect the file /afs/uncc.edu/coe/unix/opt/mgc/mosis/adk17/userware/dve/dsim.setup. The final design viewpoint configuration created by the "adkdve05" command is shown in Fig. 4.4.
Finally, save the viewpoint by clicking the "Save Design" icon in the Palette.
./ps/dve_invcom.gif
Figure 4.6: Selecting the inverter component with the navigator.
The foregoing Design Viewpoint Editor settings required to prepare a viewpoint for Quicksim simulation are summarized in Table 4.1. (Lambda is added to show an example of a number type.)
Table 4.1: Quicksim Design Viewpoint
Step Operation Name Value Type
1 Edit->Add->Primitive model technology expression
2 Edit->Add->Parameter technology ami05 string
3 Edit->Add->Parameter lambda 0.3e-6 number
4 Other parameters: see /afs/uncc.edu/coe/unix/opt/mgc/mosis/adk17/userware/dve/dsim.setup
5 Other parameters: see sdl.setup

Chapter 5
Accusim: Analog (SPICE) Simulator

Accusim is the Mentor software tool that performs analog simulations. For digital simulations, refer to Quicksim II in Chapter 4.

5.1  Preparing for Accusim with adkdve05 or adkdve12

Before proceeding, the design files must be prepared for simulation. However, the procedure is fairly complicated. To simplify matters, the command "adkdve05" (or "adkdve12") automatically runs Design Viewpoint Editor and prepares the file for simulation with Quicksim. For reference, a short overview of how this would be done manually using Design Viewpoint Editor is later provided.
The preferred method for preparing the schematic for simulation in Accusim is provided as part of the ADK design kit for MOSIS. To use this method, execute the command "adkdve05 ." or "adkdve12 ." in the directory containing the design ( ~/mentorg/intro/inv1). If you previously ran adkdve05 in the directory, you do not have to run it a second time. The "." after the command is necessary, and indicates that the current directory is the directory containing your design. For the inverter design example, change to the inverter directory, and run adkdve05 as follows:

 
 
cd ~/intro/inv1
adkdve05 .
After the script finishes running, a new directory "~/mentorg/intro/inv1/sdl" should be created along with several new files including "sdl.dvpt_1," and "sdl.Eddm_design_viewpoint.attr." These auxiliary files are hidden in Design manager, but can be seen using the UNIX "ls" command in a terminal window. These files represent the newly created design viewpoint for Accusim that was given the default name "ami05" when you ran the command adkdve05.

5.2  Simulating the Inverter Schematic with Accusim

In the Navigator pane of Design Manager, navigate to ~mentorg/intro/inv1 directory. In the directory, you should see the design viewpoint "~/mentorg/intro/inv1/accusim" that was created with the command "adkdve05." This design viewpoint file should be located under the mentorg/intro/inv1 directory and appears as a file-folder with the letters "dvpt" indicating design viewpoint. After selecting the file, right-click on the "accusim" icon to pop-up the menu and launch the Accusim application. You should see your schematic in the Accusim window as shown in Fig. 5.1. An informational terminal window is also launched and should be iconified. Use the menu-bar command MGC->LocationMap->SetWorkingDirectory to set the working directory to the design directory ~/mentorg/intro. When the Accusim window first opens, make sure that there are no error messages in the message area at the bottom of the window. Similarly, check the terminal window that was spawned.
As a different way to start Accusim, in the Tools pane of Design Manager, double-click on the "AccuSim" icon to launch the Accusim application. In the dialog box, use the navigator to select the design viewpoint "~/mentorg/intro/inv1/accusim" that was created with the command "adkdve05."
./ps/acu_win.gif
Figure 5.1: Accusim window.
In this exercise, a transient simulation of the circuit will be performed. To begin, select the command Setup->Analysis from the menu bar. In the dialog box that appears, select a transient analysis with 1 ns timesteps and a stop time of 100 ns as shown in Fig. 5.2. Alternatively, you could select the "Frequency" analysis Icon in the palette, then click the "SetupAnalysis" icon.
./ps/acu_trans.gif
Figure 5.2: Accusim: transient analysis settings.
Next, forcing functions are applied to the circuit. First, select the input port by clicking on it within the schematic. The wiring attached to the input port should become dashed, indicating that it is selected. Make sure that this is the only circuit selected (use "F2" or stroke-U or mouse-click the function-key areato unselect, if necessary). Then, click on the "Add Force" icon in the palette to begin adding a forcing function to the input port. Fill in the dialog box as shown in Fig. 5.3 to create a 50 ns pulse with 5 volt amplitude. Be sure to set the reference voltage to "//GND."
Note: it is not necessary to set a 5 volt DC force on the Vdd pin of the schematic; this is automatically done by the script file "adkdve05" that prepared the design for simulation under Accusim. To change the default supply voltage on VDD, use the command Edit->Property->Change on the menu bar to change the parameter "dcinit" to a different value.
./ps/acu_force.gif
Figure 5.3: Accusim: adding a forcing function.
To begin simulation, select the input and output ports on the schematic. (The corresponding wiring should then appear as dashed lines.) Then, click on the "Trace" icon in the palette and the analog trace window will appear.
Before running the simulation, the location of the device models for the NFET and PFET must be specified. Using the command File->AuxiliaryFiles->LoadModelLibrary from the menu bar, use the navigator to load the file $ADK/technology/accusim/ami05.mod. To move to the directory, click on the 4-arrow icon in the navigator and enter "$ADK/technology/accusim" when it prompts for a directory. Alternatively, just enter "$ADK" and navigate your way down to technology/accusim.
Finally, to run the simulation, run the command Palette->Run or MenuBar->Run->Normal from the menu bar. The resulting simulation should generate the output shown in Fig. 5.4.
./ps/acu_trace.gif
Figure 5.4: Accusim: simulation results.
( Plot/print the Accusim simulation trace of your inverter as plot P3 )
Save the Accusim setup using the command File->Simulation->SaveSetupDataOnly from the menu bar. Use the navigator to navigate to the ~/mentorg/intro directory and add the filename "acsim" to the end of the path to save the setup. The waveforms used for the forces can be saved using File->WaveformDB->Save. Again navigate to the ~/mentorg/intro directory, and append the filename "/accusimWaveDB1" to the path.
The setup can be saved using File->Simulation->SaveSetup. Navigate to the ~/mentorg/intro directory, and append the filename "/accusimSetup1" to the path.
If there are errors, use menu-bar command Report->ViewOutfile to view the output file for more details.

5.3  Measuring Currents

To add a trace for the current through a device:
  1. Unselect all parts on schematic (stroke-U or F2 key)
  2. Select a particular pin on a part through which current flows. Dont select the part (where the whole part is highlited), instead just select a pin on a part (where a 4-pointed crosshair appears on the pin). The drain on one of the FETs would be good.
  3. Right-click the mouse to get the pop-up menu and select Report to get the component instance name (i.e., /I$3/D for the drain of device I$3) plus other information.
  4. You may add the trace by right-clicking the mouse and using the pop-up menu. Alternatively, you may use the menu-bar Add->Trace .
  5. The new trace should appear in the chart.
  6. Rerun the simulation to see the results.
( Plot/print the Accusim simulation trace of your inverter with the current added as plot P4 )

5.4  AC Analysis

To perform an AC small-signal transfer function as a function of frequency, use the following sequence of commands.
Before setting up the AC analysis, you must delete the "Force" that was added in the previous section. To delete the force, unselect everything in the schematic pane, then use the mouse right-click pop-up menu Delete->Forces on selected signals.
  1. Delete any previous forces that were added
  2. Delete the old chart (close the pane)
  3. Click the "Chart" icon in the palette to get a new chart
  4. Select the "Frequency" analysis Icon in the palette
  5. Select the input signal in the schematic and click the Palette->AddForce (the "AddForce" icon in the Palette)
  6. Add a 1 volt AC with 2.3 voldt DC offest source. Leave the AC voltage 1 volt AC since small signal analysis is used regardless of the voltage, i.e., there is no clipping of voltages in AC analysis.
  7. Select the "Frequency" analysis Icon in the palette
  8. Select the input and output, then "AddTrace" if the traces are not already in the chart
  9. Palette->SetupAnalysis (i.e., click SetupAnalysis icon in the Palette)
  10. RunMode: Normal
  11. Analysis: AC
  12. SweepType: decade
  13. StartFreq: 1K StopFreq: 10G
  14. Palette->Run
  15. You may need to re-click Palette->Trace and Palette->Runto popup a new chart if it gets confused ny the time analysis in the current chart. Note that the second chart may be hidden behind the first one.
The results of AC analysis should be similar to Fig. 5.6 .
As before, you can also use the trace command from Add->Trace and Run->Run from the menu bar.
The DC voltages and currents of the circuit at the initial operating point before the AC sweep are available in the output file of the simulation. To see this report, use Report->ViewOutfile from the main menu bar. Also listed are the main parameters of the transistors in the circuit under their bias conditions. For FETS, transonductance is listed as GM, along with bias voltages and capacitances. The FET output resistance is given as an output conductance GDS. Similarly, GM, voltages, and capacitances are given for BJT's. The operating region of the FETs are also listed as being in "saturation" or "linear" region. Note that these values are at the initial operating point only.
( Plot/print the Accusim AC simulation trace of your inverter with the current added as plot P5 )
( What is the AC gain of the inverter? Q1 )
( What is the initial operating point DC output voltage of the inverter? Q2 )
./ps/acu_acanal.gif
Figure 5.5: Accusim: AC simulation results.

5.5  DC Sweep Analysis (Transfer Function)

To get a DC sweep (or the DC transfer function of a circuit), use the following sequence of commands to setup the analysis.
  1. Delete any previous forces that were added, in the schematic pane run right-click pop-up menu, Delete:Forces:all
  2. Delete the old chart (close the pane)
  3. Palette->DCAnalysis
  4. Select the input port in the schematic pane
  5. Palette->AddForce
  6. Add a 1 volt DC force to input
  7. Select the input port in the schematic pane
  8. Palette->SetupAnalysis , select DCSweep
  9. Set Source:Volt, PosNet:/IN1, NegNet://GND, From: 0 to 5 volts
  10. OK
  11. Select both the input and output ports in the schematic pane
  12. Palette->Trace
  13. Palette->Run
./ps/acu_dcxfer.gif
Figure 5.6: Accusim: DC Sweep results.

5.6  DC Operating Point

The DC voltages and currents of the circuit at the initiaql operating point before the sweep are available in the output file of the simulation. To see this report, use Report->ViewOutfile from the main menu bar. Also listed are the main parameters of the transistors in the circuit under their bias conditions. For FETS, transonductance is listed as GM, along with bias voltages and capacitances. The FET output resistance is given as an output conductance GDS. Similarly, GM, voltages, and capacitances are given for BJT's. The operating region of the FETs are also listed as being in "saturation" or "linear" region. Note that these values are at the initial operating point only.

5.7  Preparing for Accusim Using Design Viewpoint Editor

You can use Design Viewpoint Editor (DVE) to view the contents of a design viewpoint. Although you are not likely to ever edit a design viewpoint, it is useful to see what is contained in a design viewpoint.
In the Navigator pane of Design Manager, navigate to ~mentorg/intro/inv1 directory. In the directory, you should see the design viewpoint "~/mentorg/intro/inv1/accusim" that was created with the command "adkdve05." This design viewpoint file should be located under the mentorg/intro/inv1 directory and appears as a file-folder with the letters "dvpt" indicating design viewpoint. After selecting the file, right-click on the "ami05" icon to pop-up the menu and launch the DVE application. The final design viewpoint configuration created by the "adkdve05" script is shown in Fig. 4.4.

5.7.1  Preparing a Design Viewpoint From Scratch

Note: You should never need to create a design viewpoint from scratch!
Most users can safely ignore this section. The preferred method for preparing a design viewpoint for simulation is to use the command "adkdve05." See Section 4.1 for details. The following description of Design Viewpoint Editior is for reference only.
If you needed to create the design viewpoint from scratch (instead of using the command adkdve05), you would first start Design Viewpoint Editor, in the Tools pane of Design Manager, by double-clicking on the "DVE" Design Viewpoint Editor icon. This will launch the Design Viewpoint Editor application shown in Fig. 4.5. An informational terminal window is also launched; this window should be iconified. Click on the "Open VPT" icon in the Palette, and use the navigator to select the inverter component. The DVE window may need to be enlarged to see the navigator button in the dialog box that appears. In the navigator, the inverter (inv1) appears as the file-folder icon with the letter "C" inside as shown in Fig. 4.6. In the dialog box, name the viewpoint "ami05" replacing the default name, and click "OK."
Before proceeding with the simulation, the design files must be prepared for simulation using Design Viewpoint Editor (DVE). In the Tools pane of Design Manager, double-click on the "DVE" Design Viewpoint Editor icon. This will launch the Design Viewpoint Editor application shown in Fig. . An informational terminal window is also launched; this window should be iconified.
Click on the "Open VPT" icon in the Palette, and use the navigator to select the inverter component. The DVE window may need to be enlarged to see the navigator button in the dialog box that appears. In the navigator, the inverter (inv1) appears as the file-folder icon with the letter "C" inside as shown in Fig. 4.6. In the dialog box, name the viewpoint "acsim," replacing the default name, and click "OK."
Next, select the standard Accusim setup using the menu-bar command
Setup->Accusim.
The viewpoint is next customized to indicate that the model property "technology" is a primitive (lowest level in the design). From the menu bar, use Edit->Add->Primitive. In the dialog box, enter "model" for the property name, "technology" for value, "Except Flag" off, and a property type of expression.
To give the technology a value, use Edit->Add->Parameter, or click on the same icon in the Palette. In the dialog box, enter "technology" for the name, a property type of string, and enter "ami05" for in the value field. This selects the MOSIS AMI 0.5 micron process. The resulting configuration is shown in Fig. .
Note that the MOSIS technology parameter was defined at the Quicksim design viewpoint level rather than the schematic level. This allows the schematic to be used for different processes.
The setup process for design viewpoint can become rather complicated. There are other parameters set besides the two mentioned above. To see these parameters, inspect the file /afs/uncc.edu/coe/unix/opt/mgc/mosis/adk17/userware/dve/dsim.setup. The final design viewpoint configuration created by the "adkdve05" command is shown in Fig. .
The procedures for entering the viewpoint parameters are entered in the same fashion as described in the Quicksim design viewpoint case.
Finally, save the viewpoint by clicking the "Save Design" icon in the Palette.
./ps/dve_accusim.gif
Figure 5.7: Design Viewpoint configuration for Accusim.
The foregoing Design Viewpoint Editor settings required to prepare a viewpoint for Accusim simulation are summarized in Table 5.1.
Table 5.1: Accusim Design Viewpoint
Step Operation Name Value Type
1 Edit->Add->Primitive NA NA expression
2 Edit->Add->Parameter NA NA string
3 Other parameters: see $MGC_HEP/userware/dve/sdl.setup

Chapter 6
IC Station: Schematic Driven IC Layout

IC Station is the Mentor software tool that performs IC (integrated circuit) layout. It is possible to layout integrated circuits completely by hand, where each polygon for each mask is layed out explicitly. It is also possible to have the IC layout automatically generated fron schematics or VHDL descriptions. Below we describe the various methods, with particular focus on schematic driven layout (SDL).
This chapter is divided into two parts sections. In the first section, and older approach to layout is described for the AMI 0.5 micron process. In the second section, the newer layout approach to be used in AMI 0.5 micron process is described.

6.1  IC Station: Schematic Driven Layout (SDL) for AMI 1.2 Process

This section dcescribes an older layout approach for AMI 1.2 micron process. Refer to Section 6.2 for newer procedures to layout for AMI 0.5 micron process.
Do NOT use the methods in this section to layout in AMI 0.5 micron.
The schematic design files must be prepared for IC layout, much in the same fashion that the files were prepared for analog simulation using accusim. The use of the "adkdve12" script to prepare the schematic design for IC layout is first described. Then, the actual layout procedures are discussed.

6.1.1  Preparing for IC Layout Using adkdve12

If you created a simple inverter in the previous chapter using AMI 0.5 micron process, recreate the schematic for the AMI 1.2 micron process in a new directory. To do this, you have to close all Mentor tools, and restart using the command "dmgr12" to start Design Manager and then start Design Architect from within Design Manager. In this manner, Design manager will pass the proper AMI 1.2 micron environment variables to Design Architect.
Before proceeding, the design files must be prepared for simulation. However, the procedure is fairly complicated. To simplify matters, the command "adkdve12" automatically runs Design Viewpoint Editor and prepares the file for layout with ICstation. To use this method, execute the command "adkdve12 ." in the directory containing the design. The "." after the command is necessary, and indicates that the current directory is the directory containing your design.
Make sure that you have a file or directory named ämi12" when you are finished running adkdve12.

6.1.2  Schematic Driven IC Layout

Close any open Mentor tools. To run ICstation, you must run from within the special design manager "ic12." In the Tools pane of Design Manager, double-click on the "ic" icon to launch the IC Station application. When the IC Station appears, the message area just beneath the menu bar should display the text "Process: ami12(-R)," and the message area at the bottom of the window should indicate "Rule File Loaded."
Use the menu-bar command MenuBar->MGC->LocationMap->SetWorkingDirectory to set the working directory to the design directory ~/mentorg/intro. Begin creating the IC layout by clicking the "Cell Create" icon in the Palette or by using the MenuBar->File->Cell->Create command from the menu bar. Create a cell ~/mentorg/intro/inv1u12_cell by entering following data in the dialog box:
Cell create settings:
 
 

Cell name: inv1u12_cell
Attach library: (Leave this blank)
Process: $ADK/technology/ic/ami12
Rules File: $ADK/technology/ic/ami12.rules
Angle: 45
Connectivity: With Connectivity Editing
Logic source type: EDDM
EDDM schematic viewpoint: ~/mentorg/intro/inv1u12/sdl
Logic loading options: flat
 
 
The create dialog box is shown in Fig. 6.1.
./ps/icsdl_blank_create.gif
Figure 6.1: IC Station: create a new cell.
Click OK to create the cell. The IC cell window for "inv1u12_cell"will appear. In the Palette area, click on "ECO" then select Logic/OPEN to open the schematic (Palette->ECO->Open).
An alternative way to have created this cell would have been to use the Palette->Create-SDL command instead of the Palette->Create command. In both cases you need to select the sdl viewpoint for the schematic,  /mentorg/intro/inv1u12/sdl.
Select the layout pane and note the message just below the menu-bar, "Context: inv1_cell(CBC-E-0)." This indicates that the inv1_cell is being edited in CBC or "Correct by Construction" mode. It is possible to reassert the option after the Cell pane appears using the menu-bar command Context->SetCellConfig. The difference in editing modes are summarized in Table 6.1.
Table 6.1: IC Editing Modes
Mode Function
Geometry Editing (GE)
unrestricted polygon editing, no schematic updating, does not require a schematic
Connectivity Editing (CE)
unrestricted polygon editing, with schematic updating, does not prevent rule violations or conflicts with schematic
Correct by Construction (CBC)
will not allow layout that conflicts with design rules or conflicts with schematic
Click on the top of the Cell Pane (the first pane that was created) to make sure that the Cell Pane is selected and not the Schematic Pane. (Note that the main menu bar of the IC station window changes depending on which of the two panes in the window is selected.) A green "ADK" should appear as the rightmost item on the menu bar, allowing access to special added features for the MOSIS design kit. If this is not the case, there is a problem with your setup or cshrc file or the environment variables.

SDL Placing Parts

Click on the top of the Schematic Pane to make sure that the Schematic Pane is selected and not the Cell Pane. To automatically layout the chip, select "AutoInst" under the "DLA Logic" section of the Palette, Palette->AutoInst. (In some situations, it is necessary to first select the parts in the schamatic that you want to be automatically generated in the layout.) When placement is complete, a message will appear in the message area at the bottom of IC Station, "Placement Complete."
Note: placement of parts is roughly done in the same orientation as placement of the stmbols on the schematic.
Click on the top of the Cell Pane to make sure that the Cell Pane is selected. Then use the menu-bar command MenuBar->View->All, and the layout in Fig. 6.2 should be seen. The top FET is the PMOS device, the bottom NMOS. Click on the PMOS device in the Schematic Pane, and the outline of the PMOS device is highlited in the cell layout pane. Click on it again to unselect it. Similarly, if you click on the white box that outlines the NMOS FET in the cell layout pane, the NMOS device is highlited in the schematic. Use the F2 key or stroke-U to unselect all of the devices.
./ps/icsdl_lay1.gif
Figure 6.2: IC Station: automatically placed devices.
Alternative placement strategies could have been used instead of "A Inst" under the "Schem" section of the Palette. The options are summarized in Table 6.2.
Table 6.2: Device Placement Options
Option Name Function
A Inst Automatic placement of device instances
M Inst Manual placement of device instances
U Inst Placement of unplaced device instances
S Inst Select all unplaced instances
S Port Select unplaced ports
M Port Manually place ports
U port Place unplaced ports
At this point, each of the two FETS can be repositioned, if desired. To move the FETS, click on the outermost boundary of the device to select it. Then use the pop-up menu (right mouse button in the pane) command Edit->Move->Unconstrained in the Cell Pane to move the FETS as desired.
Some layers appear to be missing in the layout of the two devices in Fig. 6.2. These missing layers are hidden from view. Mentor Graphics permits a hierarchical design methodology, where higher levels of the design are composed of building blocks at lower levels. At higher levels, it is not necessary to see all of the details from lower levels, and these details are hidden from view. For instance, a circuit schematic using several operational amplifiers typically does not require inclusion of transistor-level schematic details of the amplifiers.
Click on the top of the Cell Pane to make sure that the Cell Pane is selected and not the Schematic Pane. To see the hidden details beneath the present level, select the two FET's so that their outlines are highlighted. Then, enter the menu-bar command Context->Heirarchy->Peek, and enter 99 level in the pop-up window. The cell layout should now show the hidden details as shown in Fig. 6.3. At this level, added hidden details of the transistor layout become visible. Although "peek" function will remain activated for this tutorial, it is possible to restore the cell to the state where lower layers are hidden using the command Context->Heirarchy->Unpeek.
./ps/icsdl_hide.gif
Figure 6.3: IC Station: peek, showing hidden design levels.
The different masks in the integrated circuit layout are color coded. You should see a Layer Palette in the upper right corner, since this palette is automatically added at startup. The Layer Palette should appear as shown in Fig. 6.4. Use the menu-bar command Other->Layer->AppendLayerPalette to add missing layers as needed.
./ps/icsdl_layers.gif
Figure 6.4: IC Station: Layer Palette.
If the Layer Palette was not started automatically, you would use the menu-bar command Other->ShowLayerPalette and in the pop-up window, select layers such as layers 41 through 51, corresponding to P-well through Metal 2. To select multiple layers within this pop-up menu, either drag the mouse to select the layers, or click on individual layers while holding down the control key. (Release the control key to scroll the display if necessary.) The Layer Palette is useful not only as a reference, but can also be used to select which layer is involved in editing operations such as adding diffusion regions.
In the layout of Fig. 6.2, the gates (poly) are shown as solid red. The active regions are indicated by the solid green layer, and the Metal 1 contacts for source and drain are shown as diagonal lines in blue. At the far right of the Layer Palette in Fig. 6.4, the letters "svf" appear to the right of each layer. The "s" indicates the layer is selectable, "v" indicates the layer is visible, and "f" indicates that any fill pattern assigned to the layer will be visible. To make the active region invisible, click the center mouse button on the layer in the Layer Palette. Click again to make it visible. This can be useful for viewing overlapping layers.
Check the dimensions of the red gates by moving the mouse pointer while observing the X-Y coordinates of the "Cursor:" message just below the menu bar. The gate width should be 5 lambda and the gate length should be 2 lambda.

Overflows

The two yellow lines seen between the two FETS in Fig. 6.2 are "overflows" and represent connections that have not been finshed in the layout. Click on the leftmost yellow line (connecting the two red poly regions), and the corresponding connections in the schematic will be highlighted. Use F2 to unselect the connections. The highlighting of the corresponding items in the schematic simplifies the task of laying out the circuit and reduces the likelihood of errors.

Placing Ports

From the menu-bar, run Setup:SDL and set sdl portstyles setup->processport->default before placing any ports from your schematic. Before placing ports, make a list of where all your pads go and their names, or print out the schematic. You will need to refer to this for placing the ports
Unselect everything in the schematic, then click Palette->PlacePort. (or select one port at a time and place it, but dont select ports plus schematic parts at the same time ) You will have to watch the bottom of ICstation to see the names of the current port being placed, and unfortunately they seem to be randomly chosen. After all the ports are placed the layout should look like Fig. 6.5 with the yellow overflows.
./ps/icsdl_portsplaced.gif
Figure 6.5: IC Station: Ports placed.

Adding Vias to Ports

Note that the ports are drawn in layer Metal2.port, and this is not a "real metal layer" that would result in metal when your chip is fabricated. You must add Metal2 to create "real metal" under this port. One way to do this would be to draw a metal 2 shape below ovelappint the port. A better way would be to draw a "via cell" that is comprised of a 4x4 metal2 on top of a 2x2 via layer on top of a 4x4 metal1. You could draw each layer by hand, or you can use the short-cut Palette->Via. Select the layout pane and use Palette->Via to add a via underneath every port.
Finally, unselect everything in the layout. Then select a port and its via. At the bottom of ICStation you should see a message "1 shape + 1 via selected." Then MenuBar->Connectivity->Port->AddtoPort will merge the two selected objects into members of the same port. Repeat this for each port, making sure you unselect everything before doing the next port.

PMOS and NMOS FET structure

Use the F2 key or stroke-U to unselect all of the regions in the cell. On the PMOS device, the green N-well surrounds the yellow P+select that surrounds the green active region. Inside the active region are the two bright-green white-bordered contact-to-active regions at the source and drains. Blue metal 1 regions are over the drain and source contacts. The red poly gate is in the middle, between the drain and source contacts.
On the NMOS device, the yellow P-well surrounds the green N+select that surrounds the green active region. Inside the active region are the two bright-green white-bordered contact-to-active regions at the source and drains. Blue metal 1 regions are over the drain and source contacts. The red poly gate is in the middle, between the drain and source contacts (In actual fabrication using the MOSIS N-well process, the P-wells are ignored since the p-substrate serves as the "well."
Before beginning the process of completing the layout, it may be advisable to increase the number of operations that can be "undone." Use menu-bar command Setup->IC to access the setup dialog box. In the box, change the undo level to 20 or higher.

Well Contacts

Although the two transistors in the layout have wells, they are missing contacts to the wells. These contacts are needed to provide the electrical connection for biasing the wells.
An easy way to add well contacts is by using the macros "pwc" for P-well contact and "nwc" for N-well contact. To place the N-well contact, type "nwc" in the layout pane. To place the P-well contact, type "pwc" in the layout pane. These well contacts are asymmetric, and the N-well contact should be placed abutting the top of the N-well, and the P-well contact should be placed abutting the bottom of the P-well as shown in Fig. 6.6. To see the contacts properly, use MenuBar->Context->Heirarchy->Peek 99.
After peeking the contacts, select metal 1 in the layer palette. Then Palette->AddPath to draw a 3 lambda wide metal 1 path connecting the well contacts to the corresponding sources of the devices.

Manual Poly Routing

The yellow overflow lines in the layout indicate connections that remain to be completed. Each of these missing connections must be completed using manual or automatic routing. In general, automatic routing is the safest method and least likely to create errors. Unfortunately, poly is not automatically routed, so some manual routing will have to be done in our example circuit (for the gates).
To connect the device gates, the Path method will be used. First, select the poly layer by clicking on poly in the Layer Palette. The message area right below the menu bar should then contain the message "Layer: POLY." Use the F2 key to unselect all items in the layout. Next, click on the "Path" item under the "Add" section of the Palette. (Because of the space taken up by the Layer Palette above the ECO Palette, it may be necessary to scroll down the Palette with the Page Down key or by activating the scroll bars using the pop-up menu in the palette invoked with the right mouse button.) The "ADD PA" pop-up window will appear, and click on the options button to make sure that the default poly width is 2 (lambda). Use the "Keep Options" button to retain the setting.
Click on the center near the lower end of the PMOS device at the top of the layout. After releasing the mouse button, move down to the center of the gate near the top of the NMOS device, and double-click to complete the path. Click cancel on the "ADD PA" pop-up to stop adding paths. The connection just entered should appear as a red rectangle connection the two gates, with a red centerline. The corresponding yellow overflow should also disappear, and the circuit net, or wiring, in the schematic should also be highlighted. Press the F2 key or use stroke-U to unselect the connection just made, and the red rectangle should become a red-filled rectangle.
Add another short poly section that goes left from the middle of the poly you just added (toward the input port). Note that the overflow shifts after the poly path is added. Next, draw a contact to poly using the "pc" macro, by placing the cursor over the end of the poly path and typing "pc" in the layout pane. A poly contact should be automatically drawn by the macro as shown in Fig. 6.6.
Alternatively, you could draw the poly contact by hand. To do this, follow the SCMOS rules or SCMOS_SUBM rules as appropriate. Draw a 4x4 poly, then a 2x2 contact-to-poly, then a 4x4 metal1, all centered on each other.
The metals and poly have minimum widths as part of the scmos design rules. A few of the design rules are summarized in Table 6.3. The MOSIS AMI 0.5 micron process uses the SCMOS_SUBM rules with lambda = 0.3 microns. The MOSIS AMI 1.2 micron process uses the SCMOS rules with lambda = 0.6 microns. (For historical reasons, the normal lambda=0.8 micron AMI 1.5 micron process is "squeezed" to create a lambda=0.6 micron AMI 1.2 micron process.)
For more details, see the MOSIS SCMOS design rules on the website http://www.mosis.org and http://www.mosis.org/products/fab/vendors/amis/abn/ and http://www.mosis.org/products/fab/vendors/amis/c5/ and http://www.mosis.org/Technical/Designrules/scmos/scmos-main.html .
Table 6.3: Metal Widths
Property Design Rule (units are lambdas)  
 AMI 1.2 SCMOS AMI 0.5 SCMOSSUBM
Poly1 width 2 2
Poly1 - Poly 1 spacing 2 3
Poly1 - Active spacing 1 1
Poly1 min overlap of contact 1.5 1.5
Metal1 width 3 3
Metal1 - Poly/or/Metal spacing 3 3
Metal1 min overlap of contacts/vias 1 1
Metal2 width 3 3
Metal2 - Metal2 spacing 4 4
Metal2 min overlap of via1 1 1
Metal1 - poly contact use 2×2 contact-to-poly use 2×2 contact-to-poly
Metal1 - active contact use 2×2 contact-to-active use 2×2 contact-to-active
Metal1 - Metal2 contact use 2×2 via use 2×2 via
Active min overlap of contact 1.5 1.5
Note: l = 0.3m for the 0.5 micron AMI process, thus the smallest gate is 0.6 microns (but after processing is 0.5 microns) corresponding to the minimum Poly width. l = 0.6m for AMI 1.2.

Automatic Metal Routing

In contrast to the poly layer, metal layers can make use of the automatic router to route the remaining overflows. Nevertheless, the manual routing procedure described above for poly could be used for metal routing. However, metal routing is usually done using automatic routing since manual methods are error-prone.
Next, use the automatic router to connect the NMOS drain to the PMOS drain. First, unselect everything in the layout pane. Then, select the overflow between the NMOS drain and the PMOS drain. (This overflow may be split into two overflows with a midpoint at the output port; if so, select both overflows.) Click Palette->AutoR, and when the pop-up appears, draw a large box extending liberally around your two FETS and your output port. The router is constrained to work within this area, and might not succeed if the area is too small. When finished, you should see metal paths replacing the overflows, and the overflows should disappear.
Finally, select everything in the layout pane. Click Palette->AutoR, and when the pop-up appears, draw a large box extending liberally around your entire layout. If you are lucky, all of the rest of the chip will be automatically routed. In more complex circuits, routing the whole circuit at one time rarely succeeds. It is more common to have to smal areas or a few routes at one time.
The layout with the routing completed should look like Fig. 6.6.
./ps/icsdl_path1.gif
Figure 6.6: IC Station: Layout with routing and well contacts.

DRC Design Rule Check

To check that your layout does not violate design rules, run DRC (Design Rule Check). Select the layout pane, unselect everything, and run Palette->DRCCheck. When the pop-up appears, click OK to run DRC on the entire layout (default). Alternatively, you could draw a box around the whole layout or draw a box around a portion of the layout that you want to check. At the bottom of ICStation you will get a message "DRCComplete; Results: 0" if there are no errors. If you have errors, click Palette->DRCFirst to see the first error, and Palette->DRCNext to see the rest. Fix whatever errors are found until your layout passes DRC. For more details, see the MOSIS SCMOS design rules on the website http://www.mosis.org and http://www.mosis.org/products/fab/vendors/amis/abn/ and http://www.mosis.org/products/fab/vendors/amis/c5/ and http://www.mosis.org/Technical/Designrules/scmos/scmos-main.html .

LVS

Close any open schematics using Palette->LogicClose. Then click Palette->IcTrace(M) to enter the ICTrace(M) palette. It is likely that you will have to right-click the mouse in the Palette and select the "back" option to find the ICTrace(M) item in the Palette.
In the ICTrace palette, select LVS. Use EDDM "Source Type," and use your LVS design viewpoint for the schematic "Source Name." Click Palette->Report->LVS to see the LVS report. A successful LVS should result in a "smiley face" as shown in Fig. 6.7 . Anything other than a "smiley face" is a failed LVS.
./ps/icsdl_lvssmiley.gif
Figure 6.7: Successful LVS Smiley Face.

6.2  IC Station: Schematic Driven Layout (SDL) for AMI 0.5 Process

This section dcescribes a newer layout approach for AMI 0.5 micron process. Refer to Section 6.1 for older procedures.
Do use the methods in this section to layout in AMI 0.5 micron.
Warning: Read this entire section before beginning. Otherwise, plan on spending an extra 40 hours and throwing away your design.

6.2.1  Creating an AMI05 design

If you are running a different process, switch to ami05 (run dmgr05 or ic05).
Before doing anything, create a new directory in Design Manager to contain ALL of your design! All of your new schematics and cells should be created in this new directory. Do not create subdirectories for subcircuits, keep a flat heirarchy within this one directory. Give the directory a meaningful and unique name, i.e, tpwsram1jan01u05. we have to handle many designs here! It is impossible to keep track of your chip fabrication if everyone names their design top or final or sram. as a minimum, include your initials, the thing it is (sram, adc, etc), and the technology (u05 for 0.5 micron, u12 for 1.2 micron)
After creating the directory in Design Manager (MenuBar->Add->directory), set the working directory there so you dont accidentally create files elsewhere. Every time you restart Design Manager to work on this project, set your working directory to this new directory.
Read everything below before doing a single thing!!!!!

6.2.2  Plan Ahead: Overview of File Heirarchy

You must plan ahead. Follow the design heirarchy described below. An example design heirarchy is in $ADK/lib/sdl/ami05easyfetExample.
First, your design heirarchy should have a "top layout" cell that contains all of your design with padframe as shown in Fig. 6.8. The view on the left of Fig. 6.8 is with the center peeked, and the view on the right is unpeeked.
Second, your design heirarchy should have a "main layout" cell that contains everything except the padframe as shown in Fig. 6.9. This "main layout" cell corresponds to the peeked central area of the "top layout" in Fig. 6.8. Therefore, the design of the "top layout" will include the "main layout" plus wiring to connect the "main layout" to the padframe pads.
The design heirarchy should then consist of two layers, "top layout" and "main layout."
One reason that you need these two layers in your design heirarchy is that LVS (layout versus schematic) does not work properly with padframes. And you MUST use LVS. LVS is the best way to check a layout.
A second reason that LVS is so critical in the layout of an AMI05 chip is that this process requires filler to meet the MOSIS density rules. Since incorporation of filler in a design is error-prone, LVS is needed to make sure that the added filler does not introduce errors in the layout! So, plan to have a "main" cell without padframe that can be checked with LVS, and a "top" cell that includes the padframe. Filler cells may be found in $ADK/lib/sdl/kli/newcells as "fillerx" and may be loaded and viewed in ICstation.
./ps/icami05_top.gif ./ps/icami05_topunpeek.gif
Figure 6.8: IC Station: Example AMI05 "top layout" cell with padframe.
 
 
./ps/icami05_maincell.gif
Figure 6.9: IC Station: Example AMI05 "main layout" cell without padframe.
Finally, you must do all of your simulation at the highest level of your design (the "main" level mentioned above). Do this even if you have lower level subcircuits in your design heirarchy. By simulating at the highest level, you will catch any inadvertent mis-linking of subcircuits to the highest-level design in your design heirarchy.

Plan Ahead: Ground and Power Pins

There are two issues with VDD and GND. First, PadVDD and PadGND are special pads in your top schematic that cause corresponding special pads to be added in the padframe. Second, VDD and GND are reserved global variables and should only be used in the highest-level schematic for simulation.
First, be aware that there are special pads on the padframe denoted PadVDD and PadGND that supply power to the padframe ONLY. These pads are NOT available to your circuit. (This is not exactly true, but avoid any use of the special PadGND and PadVDD pads unless you absolutely must use them.) The special PadVDD and PadGND pads are exclusively reserved for supplying power to the padframe. Use separate "analog" pads to bring power and ground in to your circuits. You may wish to bring in several such pads to power up separate portions of your circuit. Make sure that your see PadVDD and PadGND pads in your top schematic and top layout. Otherwise, your padframe will not have power, and your chip will not work.
Second, VDD and GND are reserved global symbols that can cause problems. The best approach is to only use these two schematic symbols in your top-level schematic and in your simulation schematic. Do NOT put VDD and GND in your main schematic or any lower level schematic. At all lower level schematics in your heirarchy, use pin/port names such as vdd1, vdd2, gnd1, and gnd2. You can then connect these pins/ports to the global VDD and GND in the top-level schematic. In your simulation schematic, use the special ADK VDD and GND pins on the simulation schematic and connect them to the vdd1, vdd2, gnd1, and gnd2 pins to power up your circuit for simulation. In the top schematic and in simulation schematic, the symbol for your main schematic should be used. Do NOT use a copy/paste of your main schematic. Use the symbol to minimize the chance for error. Do not name your power pins VDD or GND when you use them on your schematics or symbols or layouts. The only place there should ever be a VDD or GND is 1) the special PadVDD and PadGND pads in the top-level schematic with padframe and 2) VDD and GND to supply power in your simulation schematic.

Plan Ahead: Simulation and LVS Schematics

The foregoing method for naming power and ground pins creates a small problem for simulation. You will have to do simulation using a separate "simulation schematic" containing the symbol for your "main schematic," and with power and ground connections in this simulation schematic.
Since LVS does not tolerate multiple grounds, you will need a fourth "lvs schematic" with your gnd1, gnd2, .. connected together to satisfy LVS. If you do not do this, LVS sees the connections of ground through the substrate and complains that your grounds gnd1, gnd2 ... are connected together. Connecting them together to in your "lvs schematic" schematic makes LVS accept the layout. It may necessary to connect your grounds (gnd1, gnd2, etc.) together to a GND pin in your LVS schematic, if LVS is set up to consider the substrate as ground. This may vary from process to process, and you may need to experiment.

File Heirarchy Summary

Summarizing, you should plan as a minimum to have 4 separate schematics. An example design heirarchy is in $ADK/lib/sdl/ami05easyfetExample.
First, there should be a "top-schematic" with padframe as shown in Fig. 6.10. In this schematic, you must include all 40 pads. You must include PadVdd and PadGND to power the padframe. See the example template on $ADK/lib/sdl/padschem05, and copy it to start your own "top-schematic." The "top-schematic" will be used to create the "top-layout" with padframe. The symbol in the center of this schematic should be the "main-symbol," described next.
Second, there should be a "main schematic," without padframe as shown in Fig. 6.11. This schematic includes everything in your design, except the pads. There should not be VDD or GND symbols in this schematic. The "main-symbol" associated with this schematic will be used in the center of the "top-schematic" as shown in Fig. 6.10. The symbol should also appear in the center of the next two schematics. The "main-schematic" will be used to create the "main-layout" without padframe.
Third, there should be a "simulation schematic" for simulation. This schematic should also contain the "main-symbol" associated with the "main schematic." Do NOT copy/paste the main schematic; use the "main-symbol." This will avoid copy/paste errors and avoid forgetting to update the schematic when there are changes. Also, VDD and GND symbols should be in the "simulation schematic" to power the circuit for purposes of simulation. These VDD and GND symbols should connect to the corresponding vdd1, vdd2, gnd1, and gnd2 pins of the "main-symbol." No layout will be created from this schematic.
Fourth, there should be an "LVS schematic" for LVS. Since LVS does not tolerate multiple grounds, gnd1, gnd2, etc. should be connected together to satisfy LVS. It may necessary to connect your grounds (gnd1, gnd2, etc.) together to a GND pin in your LVS schematic, if LVS is set up to consider the substrate as ground. No layout will be created from this schematic.
./ps/icami05_topschem.gif
Figure 6.10: IC Station: Example AMI05 "top schematic" with padframe. The block in the center of the schematic is the symbol associated with the "main schematic."
 
 
./ps/icami05_mainschem.gif
Figure 6.11: IC Station: Example AMI05 "main schematic." It has no padframe.

6.2.3  Creating the "Main Schematic"

Create your main schematic (without pads) first. Give the schematic the same name as the directory, i.e tpwsram1jan01u05 . Give the schematic a meaningful and unique name. We submit many chips, and it is impossible to figure out what each design is if everyone names their design "top" or "final" or "sram." As a minimum, include your initials, the thing it is (sram, adc, etc), and the technology (u05 for 0.5 micron, u12 for 1.2 micron) .
Create your schematic ("main schematic" ... no pads) with one input port for each pin that will be on your chip. It is easiest to make all pins input ports. Since two pins must be reserved to paoer the padframe (PadVDD and PadGND), you cannot use more than 38 pins/ports. Do not use any VDD or GND symbols in the "main schematic"; replace them with ports such as VDDin1 or GNDin1. Do not use the words GND or VDD since these are global reserved variable names.
Create a symbol for the "main schematic" using MenuBar->Miscellaneous->createsymbol. Arrange the pins on the symbol exactly as you want the pinout on the chip. you will have to stretch the symbol box so that you can place 10 pins on the top, bottom, and 2 sides to match the 40 pins on your padframe. To do this, move, flip, and rotate all the pins so they are in the right places. Next, select the outline box of the symbol and add the property PHY_COMP with name/value exactly the same as the name of the physical cell created in IC station for the symbol, i.e., tpwsram1jan01u05maincell. Make sure to leave 2 empty/unused pins to allow for a GndPad and VddPad to power up the padframe and static protection. in this case your symbol would have 38 pins. Add text in the middle of the box to say what the cell is.
Stop, go back, make sure you have provision for the padframe power.
Check the schematic.
Run the command "adkdve05 ." in the directory containing the schematic.

6.2.4  Creating the "Main Layout"

Create the "main layout' cell as in Fig. 6.9 for the "main schematic" without pads as in Fig. 6.11. Give the cell the same name as the main schematic, i.e, tpwsram1jan01u05_maincell. Run the command "ic05" and click the ICstation icon in Design Manager to start ICstation for the AMI 0.5 micron process. Use the "Create-SDL" icon from the ADK Palette in ICStation to create the layout from the sdl viewpoint of your main schematic (the other methods of creating a new cell dont seem to place the ports with overflows).
Cell create settings: (Use the "Create-SDL")
 
 

Cell name: tpwsram1jan01u05_maincell
LogicSource: EDDM Viewpoint
EDDM viewpoint: ~/mentorg/intro/tpwsram1jan01u05_main/sdl
Cell Leaf Name: Source Name
Layout Directory: $HOME/mentorg/intro04
 
 
Next, make sure that the layout will fit inside a padframe! In the example main layout in Fig. 6.9, the red poly outer border was used as a guide for the outer boundary for the cell layout. Make sure the cell size is about 95 percent of the size of the inside of the padframe area. To do this, just draw a dummy padframe in an empty cell and draw poly to mark the outlines of the available area inside the padframe. Alternatively, create 4 metal1.blocking narrow rectangles at the 4 interior borders of the padframe to serve as guides for your cell. Copy your guides (without padframe) to the clipboard, and paste them in your "main layout" cell as guides for your layout.

Placing Components

Next, place all your components BEFORE placing ports. Run Palette->ECO->LogicOpen to open the schematic, if it is not already open. When the schematic opens, select all the parts, but not the ports. Then Palette->AutoInstantiate to place the parts.

Placing Ports

From the menu-bar, run MenuBar->Setup->SDL and set sdl portstyles setup->processport->default before placing any ports from your schematic. Before placing ports, make a list of where all your pads go and their names, or print out the "main-schematic" and "main-symbol." You will need to refer to the schematic and symbol as a guide for placing the ports. Place the ports roughly where they belong on the padframe, so the ports will be near the corresponding pads when you later add a padframe. Place the ports at the perimeter of your cell using Palette->place-port. As each port is placed, the bottom of ICstation shows the names of the current port being placed (unfortunately they seem to be randomly chosen). Also, if you place the ports inside a blocking layer, you may have trouble autorouting when the padframe is added later. Before placing ports, unselect everything in the schematic, then click place-port. (or select one port at a time and place it, but dont select ports plus schematic parts at the same time ) After all the ports are placed the layout should look like Fig. 6.12 with the yellow overflows.
./ps/icami05_portsplaced.gif
Figure 6.12: IC Station: Example AMI05 with ports placed.
Place a metal1/via/metal2 via (4x4 metals, 2x2 via) directly under each port BEFORE doing any routing, otherwise you will have MAJOR problems. Click Pallette->AddVia to add vias.
Stop, go back and put vias under all ports now!.
For each one of your ports, separately select the metalx.port and the via that you placed under each port, and then use MenuBar->Connectivity->Port->AddToPort to logically join metal1/via/metal2 to the port. Note that layers metal1.port and metal2.port DO NOT create metal when sent for fabrication, so you must add the metal! You should later (after routing) add more metal than that small 4x4 area to the ports, such that they protrude out from the overall cell and protrude out from the final metal1.blocking and metal2.blocking layers that you will later add to your cells. Before routing, rearrange your cells so they are fairly closely spaced, or you will waste time later when you have to add filler.
After all this work, it would be advisable to save your work at this stage as tpwsram1jan01u05_maincell_reva so you could return to this point. At a later time, if disaster strikes and you have to start over, you could recall this "reva" stage. It would also be advisable to save a new level of your design after each hour or day of work as tpwsram1jan01u05_maincell_revx, in case you need to recover from some problem. Just make sure that you save the final cell design as tpwsram1jan01u05_maincell and move all the intermediate garbage to some subdirectory "junk" when you get the final design. Otherwise, you will never be able to figure out which cell was used for your top layout when your chip arrives 4 months later.

Routing

Fill in large empty spaces of the layout BEFORE ROUTING with large metal1 and metal2 shapes that you will later remove and replace with filler. This metal will prevent routes in that region and will make adding filler a much easier task ... or you could just do it the hard way.
Next, route your cell. As before, select a few overflows in the layout and run Palette->AutoR to autoroute.

Placing Filler

Now, place filler in all the gaps in the layout. If you used the large metal1 and metal2 shapes to save room for filler, delete those shapes. AMI05 requires minimum densities of certain layers. ( See mosis website www.mosis.org for details.) Use the filler1, filler2, and filler3 cells (filler3 is biggest) as the basic filler unit. Filler cells are shown in Fig. 6.13. To add a filler cell, use the Add Cell command in the menu-bar Object menu, and type in filler3 (these should automatically be in the search path for cells). You can look at the filler cells in $ADK/lib/sdl/kli/newcells. The filler cells are connected to the substrate and can be considered as ground. These filler cells can also be used to ground hand-drawn poly by connecting to the poly in the fillers.
./ps/icami05_filler2.gif
Figure 6.13: IC Station: Example AMI05 filler cells in use and a peeked filler cell.
Stop, go back, and put the fillers in now!.
You must put the fillers into this cell, and not into the top-level cell with the padframes, because you must use LVS to make sure that you did not misplace the fillers and short circuit anything!
Poly is the layer that you must be most careful of, so you may need also to add poly to your subcells and fill in the gaps on the main cell. Try for 20 percent poly visually.

Metal Blocking

Cover your whole cell with metal1.blocking and metal2.blocking, with only your ports protruding out. If you cover the ports with blocking layer, the router wont route to them because they are blocked! On the other hand, anything you do not cover with blocking layer will be routed through, creating short circuits! At higher levels using your cell, the router doesnt see the metal in your cell! Finally, you must make the blocking layers visible to higher layers in the design heirarchy that may use this cell. To make these layers visible, select the blocking layers shapes in your cell, and use MenuBar->Object->change->aspect->both to make the blocking visible to the outside world. Otherwise the router wont see the blocking, and will route right through your cell, creating short circuits. Similarly, make the ports visible.
An example of blocking layers is illustrated in Fig. 6.14. The blue and purple rectangles surrounding the layout are the metal1.blocking and metal2.blocking layers. Note that the ports protrude outside the blocking layers so that the router is not blocked from the ports. In addition, all of the metal outside the blocking layers should be made visible (MenuBar->Object->change->aspect->both) and made part of the corresponding port (MenuBar->Connectivity->Port->AddToPort).
Finally, add text to denote each pin name on your cell and to denote the name of the cell as illustrated in Fig. 6.14. Use Metal2.blocking and Palette->AddText to add the text. Do NOT use "real layers" such as poly or metal2 to draw your text, just in case the foundry will print these layers and short circuit your layout! Also, make your text visible: MenuBar->Object->change->aspect->both.
./ps/icami05_blocktext.gif
Figure 6.14: IC Station: Example AMI05 main cell showing blocking layers around cell and metal2.blocking text at each pin.

DRC and LVS

Next, run DRC (Design Rule Check) from the palette Palette->DRCcheck. Fix any DRC errors before running LVS.
Run IcTrace(M) Palette->IcTrace(M) to do LVS and see the report. Depending where you are in the palette, you may need to right-click->back to and earlier palette to find IcTrace(M). Use your dummy schematic with all the grounds connected together for the schematic (and use the lvs viewpoint!) After LVS runs, view the LVS report by clicking Palette->Report->LVS. Anything other than a "smiley face" is a failed LVS.
After passing DRC and LVS, save the " main layout" in the top design directory (INSIDE THE DIRECTORY!). Make sure that you save the "main cell" without the padframe as tpwsram1jan01u05_maincell (or whatever.. give it a meaningfull name). Move all the intermediate garbage (tpwsram1jan01u05x's) to some subdirectory "junk" when you get the final design, otherwise you will never be able to figure out which cell was used for your layout ... spend the few minutes to clean up.
Now go back to edit your symbol created for the "main layout" and select the "box" portion of the symbol. Add the property PHY_COMP, and the enter the name of your cell. The PHY_COMP parameter tells Mentor to look for that cell name when the symbol is in a schematic. Check the symbol, ignore the errors, save the symbol, recheck and make sure you get no errors.

6.2.5  Creating the "Top Schematic"

Start accusim from dmgr after running "dmgr05." Create a top-level schematic (with pads) as shown in Fig. 6.10. See the example template on $ADK/lib/sdl/padschem05, and copy it to start your own "top-schematic." Give the "top schematic' the same name as the "main schematic," except append "top", i.e., tpwsram1jan01u05top.
If you choose not to use the $ADK/lib/sdl/padschem05 template, then manually create the schematic with 40 analog pads using MenuBar->Library->ADK->pads->ami05->Aref 10 pins at top, 10 bottom, 10 left, 10 right. Place all analog pads. Then replace 2 Aref pads with padframe power pads VddPad and GndPad, so your padframe gets power. Number the pins (Property:modify) PINXX where XX is 01 to 40, starting half-way up the right side as PIN01 and numbering consecutively counter clockwise to PIN40.
MenuBar->EditCommands->AddElectrical->Instance->SymbolbyPath to add your "main-symbol" (for the "main schematic")to the top-level schematic. Finally, wire the symbol pins to the pads. Check the schematic.
Run the command "adkdve05 ." in the directory containing the schematic.

6.2.6  Creating the "Top Layout"

Start ICstation from dmgr after running "ic05." Create the top-level layout (with pads) as shown in Fig. . Give the top-level cell the same name as the top-level schematic, i.e., tpwsram1jan01u05topcell. Use the "regular method" Palette->Create to create the cell, not "create-sdl." Use the layout viewpoint of your "top schematic" (with the pads), flat heirarchy.
Palette->Create settings (Do NOT use Palette->CreateSDL) :
 
 

Cell name: tpwsram1jan01u05topcell
Attach library: (Leave this blank)
Process: $ADK/technology/ic/ami05
Rules File: $ADK/technology/ic/ami05.rules
Angle: 45
Connectivity: With Connectivity Editing
Logic source type: EDDM
EDDM schematic viewpoint: ~/mentorg/intro/tpwsram1jan01u05top/layout
Logic loading options: flat
 
 
Make sure your working directory is set to ~/mentorg/intro/ and that your "main cell" tpwsram1jan01u05maincell is in that directory (otherwise Mentor will not be able to find your cell).
Open the schematic using Palette->ECO->Open, and select the schematic pane. Place the "main" component in the layout FIRST, using Palette->Inst (do not use autoInst since this will try to place everything).
Then use MenuBar->ADK->generate padframe . You should get the padframe with the overflows. Move your cell to center it in the padframe. Connect the overflows. Be careful not to create routing errors. Beware and closely inspect any autorouting near the padframe. Unpeek the padframe to see that the routes do not short circuit.
Run drc on the whole chip, ignore the 40 errors in the n-well of the bonding pads.
Peek the whole top-level layout (peeked with pads) and check it. Take your time to carefully inspect where the final routes went!
Save your cell, naming it appropriately, i.e., tpwsram1jan01u05topcell.
create tpwsram1jan01u05.gds from the ICsession:creategds2 palette .. please use the gds suffix!
Submit your gds file to mosis and request that mosis NOT add filler. If you did a good job, the MOSIS service check of your layout for filler (fill-pattern) should indicated that additional filler is not needed. You do not want to take any chances on what the MOSIS automatic filler-adder might do to your design. MOSIS will tell you if you dont have enough filler in your cell!
Check the email reply from your MOSIS submission for the report on insufficient density of poly, etc ... if you dont get a complaint of insufficient density, you are ok. Fix and resubmit your design if you need more filler.

Chapter 7
Digital SDL Design Using Standard Libraries

This chapter covers the schematic-driven layout and design of a digital circuit using standard libraries. In the following, the design schematic is entered at the gate level using Design Architect. These gates are selected from a library of standard gates in the Mosis Design Kit Library. Later in this chapter, the layout of the circuit is also covered.
Although digital technology is an old technology and is not likely to compete with the latest trends in analog technology, we include this chapter on digital design for completeness. :)
In the Tools pane of Design Manager, double-click on the Design Architect icon shown in Fig. 7.1. This will launch the Design Architect application. An informational terminal window is also launched; this window should be iconified.
./ps/da_icon.gif
Figure 7.1: Design Architect icon.

7.1  Schematic Entry for Digital Circuits

At the menu bar in Design Architect, check that the working directory is " ~ /mentorg/intro" by using the pull-down menu command MGC->LocationMap->SetWorkingDirectory.
Open a new schematic by using the pull-down menu command File->Open->Sheet, and entering the file name "dig1" at the end of the directory path (dont forget the leading "/".) Click the options button on the OpenSheet pop-up window to select the "New Sheet" option. An empty pane (design sheet) will appear in the Design Architect window.

7.1.1  Accessing the MOSIS SDL Library

The design will be implemented using devices from the ADK (MOSIS Design Kit) library. Select the MOSIS Design Kit libraries by using the pull-down menu command Libraries->ADKLibrary. If the ADKLibrary option does not appear as shown in Fig. 7.2, there is something wrong with your environment or with the installation of ADK.
./ps/da_mdkit.gif
Figure 7.2: Design Architect window. The command denoted by "Libraries->ADKLibrary" is shown above.
The Palette in the Design Architect window should now be the ADK Library Palette. Click on "Basic Logic Gates" item in the palette, and the gates should appear in the Palette as shown in Fig. 7.3. If you click on the "and2" item, you will see the gate symbol at the top of Fig. 7.3.
./ps/dig_gates.gif
Figure 7.3: Design Architect palette for Mosis Design Kit Basic Logic Gates.

7.1.2  Placing Parts on the Schematic

The first step is to place the devices in the Schematic Pane for the digital circuit of Fig. 7.5. Click on "and2" in the Basic Logic Gates Palette, and the symbol for a 2-input and gate appears in the pane above the Palette. Move the mouse pointer into the schematic sheet pane (without any mouse-buttons being depressed), and the symbol will appear on the schematic. Drop the gate symbol in position by clicking the left mouse button. Position the remaining devices on the schematic as in Fig. 7.5 using the inv1 devices. Leave some room between all of the devices, since the connections will be added next. Make sure not to let any symbols overlap, since this can cause problems with Accusim.
Select the Schematic Palette by using the pull-down menu command
Libraries->DisplaySchematicPalette. Now add two "portin's" and one "portout" to the schematic for the and inputs and inverter output. Click on the "Libraries" icon in the palette, then click on "Connectivitiy Symbols" to get the connectivity symbol palette shown in Fig. 7.4. You may need to zoom out (View->ZoomOut->2) on the schematic or use the scroll bars to give enough room to complete the schematic. See Section 3.1.3 for details on wiring together the parts on the schematic. See Section 3.1.4 for details on changing the names of the ports from their default values of "NET" to "in1," "in2," and "out."
./ps/dig_consym.gif
Figure 7.4: Design Architect palette for Connectivity Symbols.
Note: you do not need to add "vss," "vdd," or "gnd." This seems to be included somewhere in the lower levels of the Librarey device heirarchy.
Placement of the devices on the schematic is important. Automatic placement software that is used to produce a layout attempts to keep the devices in the same relative position as on the schematic.
./ps/dig_schem.gif
Figure 7.5: Design Architect Schematic Pane.
Finally, check your schematic by using Check->Sheet->WithDefaults. There should be no errors, but you may get warnings such as "Unable to evaluate property model" and "unable to resolve symbol expression technology." When there are no errors, save the file using the pull-down menu command File->SaveSheet->DefaultRegistration.
At this point, it is possible to create a symbol for the overall digital circuit by using the same general procedure outlined in Section 3.4.

7.2  SDL IC Layout for Digital Circuits

IC Station is the Mentor software tool that performs IC (integrated circuit) layout. It is possible to layout integrated circuits completely by hand, where each polygon for each mask is layed out explicitly. Below we describe schematic-driven IC layout for digital circuits using standard-library components.

7.3  IC Station: Digital Schematic Driven Layout

The schematic design files must be prepared for IC layout, much in the same fashion that the files were prepared for analog simulation using accusim. The use of the "sdl_prep" script to prepare the schematic design for IC layout is first described. Then, the actual layout procedures are discussed.

7.3.1  Preparing for IC Layout Using sdl_prep

The procedure for preparing the design for layout using "sdl_prep" is identical to that described in Section 6.1.1. It is also necessary to run "dsim_prep" as described in Section 4.1 to properly access the schematic. In both cases, change to the directory of the digital design "mentorg/intro/dig1" before running the two scripts, "sdl_prep" and "dsim_prep."

7.3.2  Digital Simulation

The procedure for digital simulation of the design is identical to that described in Chapter 4.

7.3.3  Digital Schematic-Driven IC Layout

In the Tools pane of Design Manager, double-click on the "ic" icon to launch the IC Station application. When the IC Station appears, the message area just beneath the menu bar should display the text "Process: scmos(-R)," and the message area at the bottom of the window should indicate "Rule File Loaded."
Use the menu-bar command MGC->LocationMap->SetWorkingDirectory to set the working directory to the design directory ~ /mentorg/intro/inv1. Begin creating the IC layout by clicking the "Cell Create" icon in the Palette or by using the File->Cell->Create command from the menu bar. Create a cell ~ /mentorg/intro/inv1/inv1_cell by entering following data in the dialog box: (NOTE: use the navigator to select the "Attach Library" item. Start with the 4-arrow button to first move to directory $SCNA20 (the scna20orbit subdirectory of the MOSIS root directory), and then follow the path until you find the library as shown in Fig 7.6. It is not a bad idea to use navigator to create the cell name and find the EDDM viewpoint, since mentor sometimes ignores the working directory setting.)

Cell create settings:
 


Cell name: dig1_cell
Attach library: $SCNA20/physical_lib/scna20orbit_lib (use navigator to find this)
Process: (Leave this blank)
Rules File: (Leave this blank)
Angle: ninety
Connectivity: Correct by Construction
Logic source type: EDDM
EDDM Viewpoint: mentorg/intro/dig1/dsim (use navigator to find this)
Logic loading options: Flat Heirarchy
Cell type: Block

./ps/dig_lib.gif
Figure 7.6: IC Station: create a new cell.
The create dialog box is shown in Fig. 6.1. Click OK to create the cell. The IC cell window for "dig1_cell"will appear. In the Palette area, click on "SDL" to load the SDL Palette. Click on "Logic:Open" in the palette to see the schematic. (In Section 6.1.2, we used a slightly different approach where we left the EDDM viewpoint field empty and had to "Logic:Set" first.) The the schematic of the digital circuit with the and gate and inverter should appear.
Reselect the cell pane. Note the message just below the menu-bar, "Context: dig1_cell(CBC-E-0)." This indicates that the inv1_cell is being edited in CBC or "Correct by Construction" mode. It is possible to reassert the option after the Cell pane appears using the menu-bar command Context->SetCellConfig. The difference in editing modes are summarized in Table 6.1.
Click on the top of the Cell Pane (the first pane that was created) to make sure that the Cell Pane is selected and not the Schematic Pane. (Note that the main menu bar of the IC station window changes depending on which of the two panes in the window is selected.)
A green "ADK" should appear as the rightmost item on the menu bar, allowing access to special added features for the MOSIS design kit. If this is not the case, there is a problem with your .login file or the environment variables. Do not change any of the settings! When you drop down the ADK menu you should see "Set QueryOnMerge" and "UseDiffusionSharing." Diffusion sharing combines series and parallel transistors into a single structure that saves space in the layout.

7.3.4  Autorouter

Click on the top of the Cell Pane to make sure that the Cell Pane is selected and not the Schematic Pane. Select back in the pop-up (right mouse button) menu of the palette to return to the "IC Palettes" palette (containing the items "Easy Edit," "Edit," etc.) Click on "Place and Route" in the palette. To automatically layout the chip, in the palette:
  1. Click on "Autofp" (use default options)
    You should see green lines outlining the floorplan.
  2. Click on "Autoplc:std cell" (use default options)
    You should see the layout of the 2and gate and inverter appear.
  3. Click on "Autoplc:ports" (use default options)
    You should see 5 ports appear (small blue/purple squares.)
  4. Click on pull-down menu bar "Connectivity->Net->Restructure->All"
    You should see yellow lines (overflows) added.
  5. Click on "Autoroute:All" (use default options)
    The yellow lines should be replaced by metal layout. If the view changes, you can use the stroke of a clockwise circle (from the top) to zoom out and counterclockwise to zoom in.
  6. Click on "PREdit:Compact" (Use Direction:down)
    The layout should compress vertically.
  7. Click on "Autoroute:Compact" (Use Direction:right) The layout should compress horizontally.
To check the design, return to the "IC Palettes" palette by selecting "Back" from the pop-up menu in the palette. Then, select "ICRules" and click on "check" to check the layout against the process design rules. Click on "Summary" to see the results if there are errors.
Save the cell layout, File->SaveCell->Heirarchy.
Use "stroke-U" or F2 to unselect everything in the schematic and in the cell. Then click on the "in1" port of the schematic to highlight the corresponding port in the cell layout. Do the same for the and gate.
Use "stroke-U" or F2 to unselect everything in the schematic and in the cell. In the cell pane, use the pop-up menu to "Select:All." Then use the menu-bar command
Context->Heirarchy->Peek with option 999 levels to view all of the layers in the layout. Then use "stroke-U" or F2 to unselect everything in the schematic and in the cell. The full layout should look like Fig. 7.7. Many additional hidden layers in the design should appear. Recall, that a heirarchical layout can hide details. See Section 6.1.2 for more information on how to display the color scheme for the layers.
./ps/dig_lay.gif
Figure 7.7: IC Station: digital circuit layout.
See Section  for information on the well contacts. These appear to be implemented already in the standard cell devices.

Chapter 8
IC Pads and Padframes

This chapter covers the layout of padframes using the built-in MOSIS Development Kit (ADK) tools. The modification of the standard padframes is also covered, including discussion of potential difficulties when changing pads on the standard padframe. Analog and digital pads are discussed.

8.0.5  Padframe Generation

Open IC Station from Design Manager and create a new cell that will be the top-level cell for your design (i.e., this will be the cell sent for fabrication). Give the cell a name such as "top-cell" that makes it clear that this is the top level if the design.
Enter the following data in the dialog box:

Cell create settings:
 


Cell name: top_cell
Attach library: (Leave this blank)
Process: (Leave this blank)
Rules File: (Leave this blank)
Angle: ninety
Connectivity: Correct by Construction
Logic source type: (Leave this blank)
EDDM Viewpoint: (Leave this blank)
Logic loading options: Flat Heirarchy
Cell type: Block

Make sure that the newly created top-level cell pane is selected. Use the menu-bar command ADK->PadframeGeneration->2micron to create a 2 micron padframe in the newly created top-level cell. View the padframe using the menu-bar command View->All.

8.0.6  Changing Digital Pads to Analog Pads

WARNING! See the potential problems due to pad asymmetries in Section 8.0.7.
To change one of the digital pads ("iopad" in the 2 micron padframes) to an analog pad, first press "F2" to unselect all items in the cell. Then, select the pad that is to be replaced by an analog pad. To select this pad, drag a box accross the majority of the pad, so that the entire pad area becomes highlighted. After selecting the pad, use the menu-bar command Object->ReplaceCell. From a terminal window, find the directory containing the 2 micron padframe cells. Note the full pathname of the analog cell (i.e., $MGC_HEP/lib/padframes/scn2.0/ic/analogpad, and enter this into the dialog box.
Overflows may appear. Add Metal1, Metal2, Metal1blkg, or metal2.blgg to correct.
See the documentation for instructions on the use of the pads (in $MGC_HEP/lib/padframes/scn2.0/docs). Note that the digital pads of separate pins for enabling input/output functionality. Also refer to the schematics of the pads (using Design Architect to read the files in $MGC_HEP/lib/padframes/scn2.0/schematic).

8.0.7  Padframe Problems

Care must be taken when using or modifying the padframes. Problems have been found, even in the unmodified padframes.
The following problems appear when using mixed analog and digital pads in the Mentor Design Kit for MOSIS padframes. The VDD and VSS power rings are shortcircuited in some situations. The problems appear both in the 2.0 micron and the 1.2 micron padframes. The analog pads were placed in the ADK padframes using Object->Replace.
The difficulty seems to stem from the asymmetry of the digital pads. The following problems may not exist, depending which side of the digital IO pad the analog pad is placed against. In the unaltered 1.2 micron standard padframe, there are two places where analog and digital pads come together. The lefthand side of the padring seems not to have the VDD/VSS short-circuit problem, but the analog/digital pad on the right hand side does have this problem. Similar problems occur due to pad asymmetry in the 2.0 micron padframe.

MOSIS 2.0m Padframe Problems

If a digital (I/O) pad is placed adjacent to an analog pad (analogpad), VSS and VDD are shortcircuited as shown below. For a bit of clarity, I have only shown Metal1, Metal2, and VIAs. The image on the left below shows the VSS (upper) and VDD (lower) rings are short-circuited when the analog pad (on left) is placed adjacent to the digital pad (on right).
In the left image below, an area of Metal1 (the furthest left such area, in blue) runs between the two power rings. Under the lower power ring, the Metal1 of the left pad meets a Metal1 area of the right pad that is connected by VIAs to the lower power ring. The Metal1 of the left pad is also connected by VIAs to the upper power ring.
The problem does not appear on the digital-digital pad case shown on the right, since the Metal1 region has no VIAs connecting it to the upper power ring.
./ps/pad_20er.gif
Figure 8.1: Padframe problems, 2 micron.

MOSIS 1.2m Padframe Problems

If a digital (I/O) pad is placed adjacent to an analog pad, VSS and VDD are shortcircuited as shown below. For a bit of clarity, I have only shown Metal1, Metal2, and VIAs. The image on the left below shows the VSS and VDD rings are short-circuited when the digital pad (on left) is placed adjacent to the analog pad (on right).
In the left image below, an area of Metal1 (in blue) runs between the two power rings. Under the upper power ring, the Metal1 of the left pad meets a Metal1 area of the right pad that is connected by VIAs to the upper power ring. The Metal1 of the left pad is also connected by VIAs to the lower power ring.
The problem does not appear on the digital-digital pad case shown on the right, since the Metal1 region has no VIAs connecting it to the upper power ring.
./ps/pad_12er.gif
Figure 8.2: Padframe problems, 1.2 micron.

Chapter 9
Fabrication, GDS-II, and Tape-Out

To tape-out from IC Station, select the ICSession pallette and click on the Translate:ICLink item. A pop-up dialog box will then appear. Make the following entries:
Another dialog box will appear; make the following entries.
If all goes well your GDSII file will be created.
It is a good idea to double-check your GDSII file using another CAD package. If you have access to Ledit, type "Ledit6" at the command prompt of a terminal window. Note the directory name that Ledit expects, and create the directory if needed. Change to the ledit directory and create a link to your layout GDSII file:
cd leditdhome
ln -s myhome/mentorg/mycell.gds mycell.gds
Then within Ledit:
Acknowledgements





The present work is indebted to a host of useful examples and tutorials including: examples from the Mentor Graphics on-line documentation, on-line tutorials by Zheng Chen at Ohio University (http://www.ent.ohiou.edu/ ~ webcad/vlsi_lab.html), on-line tutorials by Dr. Brent Nelson at Brigham Young University ( http://www.ee.byu.edu/ ), and on-line tutorials by Jack Meador, David Zar, and M. Umar Farooq at Washington State University (http://www.eecs.wsu.edu/ ~ meador/tuts/). The University Education Program area on the Mentor web site provides a fairly large number of other links to many other useful tutorials at additional Universities.
The presumed platform for this paper is a Sun SPARC/ULTRA running Solaris and OpenWindows. Some added notes deal with the CDE windows environment.

Index (showing section)


layout
     GDS-II, 9.0
     padframe, 8.0
     tape-out, 9.0

AC analysis, 5.4
Accusim
     AC analysis, 5.4
     add force, 5.2
     adkdve05, 5.1
     adkdve12, 5.1
     currents, 5.3
     DC operating point, 5.6
     DC sweep, 5.5
     device currents, 5.3
     DVE, 5.7
     DVE using DA, 5.7
     errors, 5.2
     forcing functions, 5.2
     libraries, 5.2
     models, 5.2
     MOSIS, 5.1
     overview, 5.0
     parameters, 5.7
     preparing, 5.7
     preparing with adkdve05, 5.1
     running, 5.2
     simulation, 5.2
     small-signal analysis, 5.4
     trace, 5.2
     transfer function, 5.5
     transient, 5.2
ADK libraries, 3.1
ADK menu, 6.1, 7.3
adkdve05, 4.1, 5.1
adkdve12, 4.1, 5.1
analog simulation, 5.0
automatic routing, 6.1
automatic metal routing, 6.1
autorouter, 6.1, 7.3

basic logic gates, 7.1
BoldBrowser, 1.3

CDE, 1.1
check schematic, 3.1, 7.1
color problems, 2.0
commands
     UNIX, 1.2
connectivity editing, 6.1, 7.3
connectivity symbols, 3.1, 7.1
copying files, 2.0, 2.2
correct by construction, 7.3
creating design viewpoints, 4.3, 5.7
creating directories, 2.0, 2.2
cshrc
     CDE, 1.1
current, 5.3

DC operating point, 5.6
DC sweep, 5.5
delete force, 5.5
deleting forces, 5.4
density rules, 6.2
Design Architect
     check schematic, 3.1, 7.1
     connectivity symbols, 3.1, 7.1
     digital layout, 7.2
     digital schematic entry, 7.1
     gnd, 3.1, 7.1
     MOSIS libraries, 3.1, 7.1
     overview, 3.0
     placing gates, 7.1
     placing parts, 3.1
     plotting, 3.2
     portin, 3.1, 7.1
     portout, 3.1, 7.1
     ports, 3.1, 7.1
     printing, 3.2
     saving files, 3.1, 7.1
     schematic driven layout, 3.1, 7.1
     schematic entry, 3.1
     SDL schematic driven layout, 3.1, 7.1
     selection, 3.1
     strokes, 3.3
     symbol creation, 3.4
     vdd, 3.1, 7.1
     vss, 3.1, 7.1
     wiring, 3.1
Design Manager
     copying files, 2.0, 2.2
     creating directories, 2.0, 2.2
     hidden files, 2.0, 2.2
     navigating, 2.3
     overview, 2.0
     starting, 2.1
     unusual files, 2.0, 2.2
     working directory, 2.2
design rule check, 6.1
Design viewpoint, 5.7
design viewpoint, 4.3
Design Viewpoint Editor, 4.3
Design Viewpoint Editor:creating design viewpoints, 5.7
device current, 5.3
diffusion sharing, 6.1
digital design
     sdl overview, 7.0
     schematic driven, 7.0
     standard libraries, 7.0
digital IC layout, 7.3
digital layout, 7.2
digital schematic entry, 7.1
directories, 2.0, 2.2
DRC, 6.1, 6.2
DRC , 6.1
dsim_prep, 4.1
DVE
     preparing viewpoints, 4.3
     viewing viewpoints, 4.3

editing modes, 6.1, 7.3
environment
     initialization, 1.1
     variables, 1.1
errors
     Accusim, 5.2

f2, 1.2
fabrication, 9.0
FET layout, 6.1
FET structure, 6.1
file
     GDS-II, 9.0
filler, 6.2
forcing functions, 5.2
function keys, 1.2
     F2, 3.1

gates, 7.1
GDS-II, 9.0
gnd, 3.1
GND pads, 6.2
ground, 3.1, 7.1
ground pads, 6.2
ground pins, 6.2

heirarchy, 7.3
help
     on-line, 1.3
hidden files, 2.0, 2.2
hidden layers, 6.1, 7.3
hierarchy, 6.1

IC layout, 6.1, 7.3
IC Station, 6.1
     ADK menu, 6.1, 7.3
     ami12 process, 6.1, 6.2
     ami12 SDL, 6.2
     Autofp, 7.3
     automatic layout, 6.1, 7.3
     automatic metal routing, 6.1
     Autoplc, 7.3
     Autoroute, 7.3
     autorouter, 6.1
     cell creation, 6.1, 7.3
     Compact, 7.3
     connectivity editing, 6.1, 7.3
     correct by construction, 6.1, 7.3
     design rule check, 6.1
     diffusion sharing, 6.1, 7.3
     digital IC layout, 7.3
     digital layout, 7.3
     DRC, 6.1, 6.2
     DRC , 6.1
     DVE, 6.1, 7.3
     editing modes, 6.1, 7.3
     FET structure, 6.1
     filler, 6.2
     heirarchy, 7.3
     hidden layers, 6.1, 7.3
     IC layout, 6.1
     Layer Palette, 6.1
     layout, 6.1, 7.3
     layout part placement, 6.1
     logic source, 6.1, 7.3
     LVS, 6.1, 6.2
     metal, 6.1
     metal blocking, 6.2
     MOSIS menu, 6.1, 7.3
     overflows, 6.1
     part placement, 6.1
     path, 6.1
     placement, 6.1
     placing components, 6.2
     placing ports, 6.1, 6.2
     poly, 6.1
     poly routing, 6.1
     preparing, 6.1, 7.3
     routing, 6.2
     schematic, 6.1, 7.3
     schematic driven layout, 7.3
     set query on merge, 6.1, 7.3
     standard cells, 7.3
     text, 6.2
     undo, 6.1
     well contacts, 6.1
     wiring, 6.1

keyboard, 1.2

Layer Palette, 6.1
layout, 6.1, 7.3
layout part placement, 6.1
logic gates, 7.1
logic simulation, 4.0
login
     .login file, 1.1
LVS, 6.1, 6.2

Main Layout, 6.2
Main Schematic, 6.2
measure current, 5.3
metal, 6.1
metal blocking, 6.2
MOSIS libraries, 3.1, 7.1
mouse, 1.2

on-line help, 1.3
operating point, 5.6
overflows, 6.1

padframe, 8.0
pads, 8.0
palette scroll bars, 6.1
parameters, 4.3, 5.7
part placement, 6.1
path, 6.1
placement, 3.1, 6.1, 7.3
placing components, 6.2
placing gates, 7.1
placing parts, 3.1
placing ports, 6.1, 6.2
placing vias, 6.1
plotting, 3.2
poly, 6.1
poly routing, 6.1
port names, 3.1, 7.1
portin, 3.1, 7.1
portout, 3.1, 7.1
ports, 3.1, 7.1
power pads, 6.2
power pins, 6.2
printing, 3.2
printing schematics, 3.2

Quicksim
     add trace , 4.2
     adkdve05, 4.1
     adkdve12, 4.1
     delete trace , 4.2
     DVE, 4.3
     forces, 4.2
     input signals, 4.2
     MOSIS, 4.1
     overview, 4.0
     parameters, 4.3
     preparing, 4.3
     reset, 4.2
     run, 4.2
     running, 4.2
     simulation, 4.2
     trace signals, 4.2

routing, 6.1, 6.2
rule check, 6.1

saving files, 3.1, 7.1
schematic, 7.3
schematic check, 3.1, 7.1
schematic driven layout, 3.1, 7.1
schematic entry, 3.0
schematic part placement, 3.1
scroll bars, 6.1
scrolling, 6.1
SDL
     layout part placement, 6.1
     part placement, 6.1
     placement, 6.1
SDL schematic driven layout, 3.1, 7.1
set query on merge, 6.1, 7.3
small-signal analysis, 5.4
softkeys, 1.2
standard libraries, 7.0
strokes, 3.3
symbol creation, 3.4

tape-out, 9.0
text, 6.2
time analysis, 5.2
Top Layout, 6.2
Top Schematic, 6.2
transfer function, 5.5
transient analysis, 5.2

undo, 6.1
UNIX
     commands, 1.2
unusual files, 2.0, 2.2

vdd, 3.1
VDD pads, 6.2
vias, 6.1
vss, 3.1

well contacts, 6.1
wiring, 3.1, 6.1
working directory, 2.2



File translated from TEX by TTH, version 3.61.
On 27 Sep 2004, 16:14.