UNC Charlotte Agilent ADS Tutorial (Dig Comm example)

Overview

(Link to some discussion on the need for channel coding/error: Here)

This example uses ADS in digital signal processing to simulate a simple communication system.The ystem consists of a random binary source,modulater (in this example NRZ), Additive White Gaussian Noise Channel, and a reciver. then the same system was simulated after using channel coding by adding a convolutional encoder and a viterbi decoder. the simulation results show how channel coding reduces errors in the system and still uses less energy.

  • Start the software: by right clicking on the mouse

    mosaic > Engineering > ECAD-VLSI >ADS you should get the starting window:

  • From main widow choose "Options" then "advanced design system setup" you will get the following dialog box.

    Choose "Dsp Design" then Ok.

    Note: When changing system setup you have to exit the program and then run it again in order for the changes to take effect.

  • download the following tar file ( you may need to hold down the shift key while you click on the link): rhadba.tar

  • Run ADS.

  • Go down through the directory tree to ads/viterbiprj/encoder_decoder_prj.dsn and double click that design file, you should see:

  • Double-click the schematic in the right half of the window and the following schematic should appear.

    The schematic of the system

    This contains two simple diagrams. The first one contains a binary source (B2),which generates binary bits randomly. In this block you can control the bit probability. This binary source is fed to a Non_Return_toZero block(L2), where the bits are mapped into '-1' for digital "1" and '1' for digital "0". The TKplot is a display component in ADS. The first plot which is labled by "input1" and is connected to the binary source displays the binary bits coming out of the source. After the NRZ block the signal goes through the channel. The channel is Additive White Gaussian Noise Channel AWGN(C16).In the channel the noise is added to the signal and the effect of the noise on the signal depends on the Ratio of the bit energy Eb to one sided power density of the nois N0. The parameter Eb/N0 is controlled in this block. After the channel in the first diagram a test block (T5) will check the incoming signal and compare it to a constant which is set to a zero here; if the coming sample is less than or equal to zero then it is a digital "1" otherwise it is a digital "0". And a plot labeled with "output1" will display the output.

    Note: In Dsp it is required to have a sink controller at the output of the design, in this example the plot is the sink.

    The second diagram has also a binary source (B1). After the source the bits are fed to the convolutional encoder (C9) where they are encoded into channel symbols before they are being transmitted over the channel, which is also AWGN (C7). After the channel the message bits ( added to the noise in the channel) go to the viterbi decoder which decodes the message bits. The plot, labeled "output2" will display the output of the decoder. After simulation starts, all plots display the data.

    Note: In the system where the encoder/decoder are used there is a delay between the input and the output, for a delay component with delay of 15 is used, between the source and the plot. Thus it will cause a delay in the input to be able to compare the same samples at a specific time instant.

    The delay component is not shown in the schematic above. When you do the simulation, go to (numeric, control) library, click on the delay componenet, then click on the schematic. Put it between the source and the plot of the input.

  • Now to start the simulation click the "gear" icon (shown below) in the upper right of the window to simulate.

    Simulation results:

    By looking at the following figures you can see the effect of the Eb/N0 on the data transmission; decreasing this parameter from 6dB to 0dB caused more errors in both channels due to the increased noise (NO) relative to signal energy (EB). But the most important to notice is that the coded channel has less errors than the uncoded case. (This is why coding is used in communication systems -- you get less error for the same signal-to-noise ratio.) Actually when Eb/N0 is 6 dB the coded channel has almost zero error .

    The above figure shows the effect of the noise on the signal. The top signal is the input to the AWGN block in the lower schematic (the coded channel schematic). The bottom signal is the output of the AWGN block in the lower schematic (the coded channel schematic) when the EB/N0 =6 dB.

    Note: To get the figure/plots above, you must place a TkPlot block at the input and output of the AWGN block.

    The above figure is Comparision of the input and the output of the first diagram (uncoded channel) when the EB/N0 =6 dB (lownoise).

    The above figure shows the input data (top) and final recovered and "re-digitized" output data (bottom) for the upper schematic (the uncoded channel schematic) when the EB/N0 =6 dB. The top signal is the output of the binary source (B2 in the schematic) and the bottom signal is the output of the receiver, the TestLE block T5 in the Non-Coded Channel block.

    The above figure is Comparision of the input and the output of the second diagram (coded channel) when the EB/N0 =6 dB (lownoise).

    The above figure shows the input data (top) and final recovered and "re-digitized" output data (bottom) for the lower schematic (the coded channel schematic) when the EB/N0 =6 dB. The top signal is the output of the binary source (B1 in the schematic) and the bottom signal is the output of the receiver, the CDMAViterbi block C8 in the Coded Channel block.

    The above figure is Comparision of the input and the output of the first diagram (uncoded channel) when the EB/N0 =0 dB (highnoise).

    The above figure shows the input data (top) and final recovered and "re-digitized" output data (bottom) for the upper schematic (the uncoded channel schematic) when the EB/N0 =0 dB. The top signal is the output of the binary source (B2 in the schematic) and the bottom signal is the output of the receiver, the TestLE block T5 in the unCoded Channel block.

    The above figure is Comparision of the input and the output of the second diagram (coded channel) when the EB/N0 =0 dB (highnoise).

    The above figure shows the input data (top) and final recovered and "re-digitized" output data (bottom) for the lower schematic (the coded channel schematic) when the EB/N0 =0 dB. The top signal is the output of the binary source (B1 in the schematic) and the bottom signal is the output of the receiver, the CDMAViterbi block C8 in the Coded Channel block.

    More Simulation results:

    For more visibility of errors the input was set to all "1's" and the outputs of both diagrams were compared for both values of Eb/N0 0dB and 6 dB.

    The above figure is a Comparison of the coded and uncoded channel outputs (after the receiver) when input equal 1 (prob of '0' is 0) and Eb/N0 = 6 (i.e., low noise).

    The above figure is a Comparison of the two outputs when input was set to all "1's" (prob of '0' is 0) and Eb/N0 = 0 (i.e., high noise).

    Other Helpful Tips and Info:

  • You can choose component library from component pallet list (bthlib) on the top left of the schematic window.

    Here is a list of the components used in this example:

    1- Binary random bits output (common components library)

    This component generates output binary bits with bit probability defined by probability of zero and this can be in the range of 0 to 1. By double clicking on the component in the schematic you get a window where you can change the parameters of this component, which is here bit probability.

    2- Logic to NRZ block (signal converters library)

    This component converts the logic level to NRZ level. In this example logic '1' is encoded into -1 and logic '0' is encoded into 1.

    3- Bit-By-Bit convolutional encoder (CDMA channel codes library)

    The encoder type in this example is (1/2 K 3 g0 05 g1 07). The rate is 1/2 The constraint length is 3 g0 (05=101) gives the polynomial of the first modulo 2 adder g1 (07=111) gives the polynomial of the second modulo 2 adder.

    4- Delay component (Numeric, control library)

    This component delays the input from output by N samples.

    5- AWGN channel (CDMA test library)

    Additive white Gaussian noise channel, in this component the noise of the channel can be controlled by changing the parameter EbN0 Ratio.

    6- Bit-By-Bit Viterbi decoder for convolutional encoder (CDMA channel codes library)

    The decoder uses the same parameters as the encoder (1/2 K 3 g0 05 g1 07). For more information about Viterbi decoder check to the following link: http://pweb.netcom.com/~chip.f/Viterbi.html

    7- TKPlot (interactive control and display library)

    Displays the input versus sample number.

    8- DF, DataFlow (controllers library)

    This controller is required for signal processing simulation.