Overview

NOTE: Use the Project Report Template and  keep answers to questions on consecutive sheets of paper with all plots at the end.

IN NO CASE may code or files be exchanged between students, and each student must answer the questions themselves and do their own plots, NO COPYING of any sort! Nevertheless, students are encouraged to collaborate in the lab session.

Only turn in requested plots ( Pxx ) and requested answers to questions ( Qxx ).

Part 1

Note that this is the same experiment as the pulse experiment from project 3, except now we are using a frequency sweep instead of pulses. Things get a bit more complicated compared to Project 3, since we have mismatches on both ends of the line.

Go down through the directory tree to  RFcourse2012_proj3_wrk and double-click it to open the workspace

Open design p2txline2,  and the following schematic should appear.

Save a snapshot of the schematic and paste it into your report.    ( P1 )

Make sure that your plots, component values, legends, axes, and fonts are legible in your report!

Note that the S-parameters are plotted only from the perspective of the TERM devices, so the reflected power that is plotted is only that reflected back to the left TERM.

Draw a schematic on a sheet of paper with a 50 ohm 2 volt rms source and a load comprised of the left-hand 50 ohm resistor in parallel with the answer to Q13. At the S11 dip near 14 MHz, this is a good model of the circuit since the transmission has transformed the impedance (we cant use the previous low frequency model anymore!). Questions Q14 - Q20 relate to hand calculations using this hand-drawn schematic.

Calculate the voltage across the 50 ohm resistor in parallel with the Q13 calculated resistance near 14 MHz in your hand-drawn schematic? ( Q14 )

Calculate the power in mW delivered to the Q13 resistance near 14 MHz in your hand-drawn schematic.? ( Q15 )

Calculate the maximum power available available from the source (i.e., replace the 50 ohm resistor and Q13 resistance with a single 50 ohm load)? ( Q16 )

Calculate how many dB down the power in Q15 is relative to Q16 near 14 MHz? (10 log10( Q15/Q16 ) ) ( Q17 )

Consider that all the power in the Q13 resistance near 14 MHz must be dissipated in the right-hand TERM and right-hand 50 ohm resistor (the line is lossless). And since the voltage across these two resistors is the same, and they have equal resistance, the total power must be equally split between them.

Considering this, and the answer to Q17, calculate how many dB down is the power delivered to the right-hand TERM relative to the maximum power available from the source; hint: your answer should properly relate to the S21 plot P2 at 14 MHz ? ( Q18 )

Using the Q13 impedance in parallel with the left-hand 50 ohm resistor, calculate the effective load resistance seen by the left-hand TERM at 14 MHz (as shown below)? ( Q19 )

From the foregoing answer, calculate the return loss of the impedance as seen by the left-hand TERM at 14 MHz (this should correspond to S11 at 14 MHz)? ( Q20 )

Change the S-parameter box in the ADS schematic to a stop frequency of 20 MHz by double clicking the S parameter box on the schematic. Rerun the simulation.

Click the "smith plot" icon in the data plotting window.

Drop the plotting box in the visible area, and in the pop-up window:

Select DataSet -> S(1,1) -> Add
(only plot S11 on the Smith chart)

Click on the plot options, click Coordinate->both, select Grid, and select admittance line type as long dash, and pick a green/blue shade color and red/yellow shade for impedance. Click OK and the Smith Chart should appear. To figure out which end of the curve is at what frequency, Select Marker->New from the Dataplot menu bar and click on one end of the plotted curve. Then Edit->Undo to delete the marker. The Smith chart should be similar to below:

Part 2

In this part, we will experimentally determine the wavelength and impedance of a microstrip line of width 0.025 inches (25 mils) on a 0.05 inch (50 mils) thick epoxy-fiberglas FR4 board (apologies to the metric system ...). This is a good way to check your microstrip line impedance for future projects.

Go down through the directory tree to p2txline3, and double click that design file, and the following schematic should appear.

Double-click the "gear" icon in the upper right of the window to simulate.

Click the "rectangular plot" icon in the pop-up data plotting tool.

Select the plot options to plot S11 and S21 from -30 to 0 dB in 3 dB steps.

Print the S-parameter plot and turn it in. You should have a plot of both S11 and S21. S11 should have a minimum (or null) near 30 MHz. ( P5 )

What is the electrical length in wavelengths of the line at the minimum of S11 near 30 MHz??
(you should be able to figure this out from the schematic and P5 alone, but you can also confirm this from the transmission line geometry using linecalc to double-check your answer) ( Q26 )

What is the peak value of S11 near 15 MHz? ( Q27 )

What is input impedance looking into the left end of the line at the peak value of S11 near 15 MHz (as shown below)?
(Hint: is the impedance looking into the line at its largest or smallest value there?) ( Q28 )

Part 3

In this part, we design matching networks.

Design a 2-element matching network to match a load of 250 ohms in series with a 2 nH inductor into 50 ohms at 4 GHz. Proceeding from the load, use a shunt inductor then a series capacitor for the matching network. (use file p2match1 as a starting point and find the proper values for the 1000 pF capacitor and 1000 nH inductor).

For the load alone (as shown below with no matching network), Plot the the Immitance Smith chart  from 3 to 5 GHz., and make sure to add a Marker at 4 GHz ( P7 )

Design the matching network as shown below. 

What are the final design values for the matching network inductor (nH) and capacitor (pF)?. ( Q32 )

Part 4

For the past 4 months, you have been designing the world's greatest 4 GHz amplifier chip with 300 ohm output impedance and only 0.05 pF stray capacitance ... a perfect impedance match to the 300 ohm antennas you bought last month for the prototype radios!

To your horror, your manager comes into your office and says that the president of the company insists that you package your chips into the packages he bought from a friend on a fishing trip. The packages are not very good for RF. After the obligatory bond-wire inductance of 2 nH connecting your chip to the package bond area, they have a stray capacitance of 1 pF to ground and another 1.5 nH series inductance because the pins are quite long ... And if that wasnt bad enough, the president traded all of your 300 ohm antennas for a box of fancy 50 ohm antennas ... so you now need a 50 ohm output!

To make matters worse, your manager says the program is over budget so you cant use any inductors or capacitors because they will cost too much.  He insists that you can only use microstrip transmission line sections laid out as foil patterns on the system board.

Based on the great stuff you learned in RF class, you save the day by matching the antenna with a single little piece of microstrip ... and the boss gives you 10,000 Enron stock options as a bonus.

A schematic of the whole situation is shown below.  You need to make the impedance look like 50 ohms looking into the transmission line from the left. (also see the really handy file p2match3)

Plot the the Immitance Smith chart for the chip alone (the 300 ohm and 0.05 pf) from 3 to 5 GHz. ( P15 )

Plot the the Immitance Smith chart for the chip in the package (the chip plus the two inductors and 1 pF, with no transmission line matching network) from 3 to 5 GHz. ( P16 )

Notice what the package did to the chip!
The package is so bad, it almost took the impedance from an open circuit to a short circuit ...

What are the values for the microstrip matching network length (meters) and width (mils)?. ( Q36 )

Printout the schematic of your final circuit. (including matching network along with the load, ie., the chip plus the two inductors and 1 pF). ( P17 )

Plot the the Immitance Smith chart for the matched load from 3 to 5 GHZ (label start and stop frequency). ( P18 )

Plot S11 (-30 to 0 dB) for the matched load from 3 to 5 GHZ. ( P19 )

Over what frequency range is your return loss better than 10 dB?. ( Q37 )

Sketch your transmission line to 1:1 scale. ( Q38 )

Part 5

• Run the Cadence6 software
• Open your 2-resistor voltage divider schematic from the previous project in the Cadence 6 software, by double-clicking the schematic view of resDiv_cell in the Library Manager tool.
• Change both resistors in the schematic to 100 ohm resistors from the "ami05_c6_customlib"
  
• Make sure that none of your pins have names that could interfere with global names/variables.  NEVER name a pin "gnd" or "vdd" or "vcc" or "vss"
  
• Check the schematic in Schematic-XL tool using MenuBar::Check::CurrentCellView (yellow arrow below) and make sure no errors are reported in the CIF window
  
• As shown below, launch the Layout XL tool (red arrow below)
• In the popup window, select create new (blue arrow below)
  

• Print out your new schematic. ( P20 )

• In the Layout XL window, create a new layout using MenuBar::Connectivity::Generate::AllFromSource as below

• In the popup options windows, check the tabs for the options (blue arrows below) and make sure PR boundary (place and route boundary) is turned off as below (red arrow below)
• Note that all of the pins from your schematic will be created as metal1 0.9x0.9 micron pins (yellow arrows below)
  

• The devices from the schematic should now appear in the layout
  
• As before in Layout XL, use MenuBar::Options::Display to set the "Display Levels" to 0 to 30, and to set the check buttons "on" for "Pin Names" and "Instance Pins."
• If you click on a pin in the layout or schematic, the corresponding item should also be highlighted
  
• Selecting a pin in the layout highlights a pin in the schematic (blue arrow below)
• Selecting a resistor in the layout highlights a resistor in the schematic (yellow arrow below)

• Activate the annotation bowser pane using MenuBar::Window::Assistants::AnnotationBrowser
• Then, use MenuBar::Connectivity::Nets::ShowAllIncompleteNets to see the nets that must be connected, as illustrated below 
• You can move devices by typing "m" in the layout area
  
• Then, move your pins and devices into positions approximately as in the schematic, where the nets will be easy to connect and wire, as shown below 

• Print out your preliminary layout with "fly lines" of nets visible as above . ( P21 )

• Select metal1 on the LayersPalette in the left side of the Layout XL window (red arrow below), then type "p" when your mouse is in the layout area to create a metal1 path.   (Alternatively use MeuBar::Create::Shape::Path)
• Connect your circuit as illustrated below using metal1 paths
• Experiment with typing "r" in the layout area to draw a metal1 rectangle
  

• Print out your final layout as above. ( P22 )
  

• When you finish wiring the layout, run DRC (design rule check) using MenuBar::Verify::DRC as  shown below
• Make sure no errors are present by inspecting the message in the CIW window (red arrow below)
  
• For  a list of rules see MOSIS.com ON Semiconductor C5N SCMOS_SUBM rules

• Take a snapshot of your CIW output for DRC showing "Total errors found: 0" as above. ( P23 )

• When you finish DRC, run extraction (extract schematic from layout) using MenuBar::Verify::Extract as shown below
  
• Make sure no errors are present again by inspecting the message in the CIW window (red arrow below)

• When you finish extraction, run LVS (layout versus schematic) using MenuBar::Verify::LVS as shown below
• Use the "form contents" option (green arrow below)
  
• Use the browse buttons (yellow arrows below) to navigate to the schematic view and extracted views of your design
• Check that the proper files and views are loaded into the form (red arrows below)
  
• Make sure no errors are present again by inspecting the message in the CIW window to see the message "netlists match"
  

• If your design layout matches your schematic, you should get a netlist match popup as follows
• UNTIL YOU SEE THE FOLLOWING MESSAGE, YOUR DESIGN IS INCORRECT!
  

• Repeat the DRC, extract, and LVS steps on revisions of your design until you get the above message

• The LVS output file often has good information for debugging errors
• You should always check the output file, as below, even if you get the "netlists match" popup
  
• To access the LVS output file, click the output button (red arrow below)
  

• Take a snapshot of your LVS output window as shown above showing "the netlists match" as above.  MAKE SURE that you include the full output up through the "netlists match" line (blue arrow above), and include the full file name of your design (green arrow above) ( P24 )

Do not add extraneous pages or put explanations on separate pages unless specifically directed to do so. The instructor will not read extraneous pages!

Only turn in requested plots ( Pxx ) and requested answers to questions ( Qxx ). All plots must be labeled P1, P2, etc. and all questions must be numbered Q1, Q2, etc.  YOU MUST ADD CAPTIONS AND FIGURE NUMBERS TO ALL FIGURES!!