Layout of IO pad showing connections.
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Simplified schematic.
Larger view.
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Note: before using any analog pads, see Analog padframe errors Most of the information below pertains to digital I/O pads.
The pads used in the padframes for 2 micron MOSIS are given in the file scn20-pads.doc supplied with the Mentor kit in the directory $MGC_HEP/lib/padframes/scn2.0/doc, and a schematic is found in directory $MGC_HEP/lib/padframes/scn2.0/schematic.
For convenience, a gif-file of 2 micron digital I/O pad schematic is given here.
To use the digital I/O pads, the ENABLE Pin must be set to Vdd (5V) or Vss (ground). The state of the ENABLE pin determines the behavior of the pad according to the following table.
ENABLE I/O Pad behavior ---------- -------------------------------------------- set to Vdd (5V) The on-chip signal at IN_OUT1 is sent to the outside world set to Vss (Gnd) The signals from the outside world are sent into the chip at OUT_IN1, OUT_INB, and OUT_IN_unbufferedThe pins on an iopad are shown below, along with a simplified schematic. The pad notation unfortunately is a bit cumbersome.
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Layout of IO pad showing connections.
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Simplified schematic.
Larger view.
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