Useful Layout Tips


(in no particular order)

Text is CMOS Circuit Design ..., Baker, Li, Boyce

  • WARNING: S/R Flipflop is WRONG in 1.2 micron library!! For set, reset, set/reset flip flops the set line is async and active low. The reset line is async and active high. This may differ from what their respective symbols would lead you to believe. The one known bogus one is the flipflop with both set and reset.
  • Text chapter 15, layout

  • Text page 30, resistance of long poly runs is calculated from MOSIS ohm/square for poly.
  • Use contacts and metal to reduce resistance
  • Generally don't rout in poly!!
  • Beware of compaction or moving parts that may stretch poly runs
  • See also the article on adding contacts to decrease series resistance of capacitors on page 133.
  • Text page 30, same as above comments except apply to N+ diffusions and P+ difusions in drains, sources, etc.
  • Text page 30, same as above comments except apply to substrate and well contacts and resistances
  • Text page 219, laying out large FETs.

  • Text page 56, crosstalk in close lines.
  • Text page 57, inductance and ground bounce.
  • Text page 295, power distribution.
  • Text page 297, power decoupling capacitors.

  • Text page 215, susceptibility of output stages to latchup.
  • Text page 215, guard rings and latch-up. (See also text by Weste and Eshraghian, Priciples of Vlsi Design). As a practical guideline for placing substrate and well contacts to prevent latchup, look at the layouts of some of the digital gates included in the library.
  • Text page 137, guard rings around analog circuits to prevent noise from coupling into the circuit.

  • Precision layout tricks, p. 139.

  • Text page 219, laying out large FETs.
  • Text page 218, driving large loads
  • Text page 209, ring oscillator.

  • Small resistors are susceptible to large tolerance variations
  • Autorouter cna make errors. These appear to be especially problematic when routing "unrouted overflows". Watch these carefully.
  • Save your project often!!
  • Don't trust anyone else's work (don't trust your own)
  • Beware the large collector resistances of NPN devices. At high (1 mA) current, significant voltage drop can occur across this unavoidable internal parasitic resistance.

  • MOSFET Behavior
  • Triode region, text p. 94, 165
  • Saturation region, text p. 96, 165
  • Parameters, text p. 99
  • Analog models, text p. 165

  • BJT's, Chapter 16.