AMI05 notes for Mentor Graphics ADK

AMI05 notes for Mentor Graphics ADK, Feb 2002

Warning:
Read this entire page before beginning. Otherwise, plan on spending an extra 40 hours and throwing away your design.

Creating a design

if you are running another process, switch to ami05:
see the website instructions.

before doing anything, create a directory to contain all of your design

ALL of your design! Schematics and cells should be there.

give the directory a meaningful and unique name, i.e, tpwsram1jan01u05. we have to handle many designs here!
think of what happens if everyone names their design "top" or "final" or "sram"
as a minimum, include your initials, the thing it is (sram, adc, etc), and the technology (u05 for 0.5 micron, u12 for 1.2 micron)

after creating the directory in design manager (Add:directory), set the working directory there so you dont accidentally dump files elsewhere. Every time you restart dmgr, set your working directory there

PLAN AHEAD!!!!!!!!!!!!!!!!!!
Read this entire page before doing a single thing!!!!!

First you must plan ahead, you should have a top-level layout that contains all of your design with padframe (here is top-level layout "peeked" with pads a, and another cell (main cell) that contains everything except your padframe.

LVS does not work with padframes.
you MUST use LVS and you MUST use fillers. (Find these fillers in ADK/lib/sdl/kli/newcells as fillerx)
LVS will make sure the fillers dont clobber your layout and create short circuits!

It is common to want to bring out several ground pins and several power pins for various sub-circuits. this requires the following special treatment:

power supplies are a tricky problem if you want special power pins taken to analog pads.
you will have to name them vdd1, vdd2, etc ...
dont name them vdd since that is a global variable

if you use multiple ground pins, that will be tricky too. name them gnd1, gnd2, ...

the above power and ground tricks makes simulation a problem.
you will have to do simulation using a separate schematic containing the symbol for your "main-schematic", and with power and ground connections in that (3rd schematic)

lvs doesnt like multiple grounds, so you will need an "lvs" schematic (4th schematic) with your gnd1, gnd2, .. connected together to fool lvs.
(lvs sees the connections of ground in the substrate and complains gnd1, gnd2 ... are connected together ... so connecting them in your dummy lvs schematic makes lvs happy )

create your main schematic (without pads) first give the schematic the same name as the directory, i.e tpwsram1jan01u05

first create your schematic (main schematic ... no pads) with one port for each pin that will be on your chip. also, remove any power or grounds in the circuit and replace thim with ports such as VDDin or GNDin. Dont use the words GND or VDD since these are global reserved variable names.

give the schematic a meaningful and unique name, i.e, tpwsram1jan01u05.
we submit many chips, and it is a complete nightmare to figure out what each design is.
think of what happens if everyone names their design "top" or "final" or "sram"
as a minimum, include your initials, the thing it is (sram, adc, etc), and the technology (u05 for 0.5 micron, u12 for 1.2 micron)

create a symbol Miscellaneous:createsymbol. arrange the pins on the symbol exactly as you want the pinout on the chip you will have to stretch the symbol box so that you can place 10 pins on the top, bottom, and 2 sides. tediously, move, flip, and rotate all the pins so they are in the right places.

select the outline box of the symbol and add the property PHY_COMP with name/value exactly the same as the name of the physical cell created in IC station for the symbol.

make sure to leave 2 empty/unused pins to allow for a GndPad and VddPad to power up the padframe and static protection. in this case your symbol would have 38 pins.

Stop, go back, make sure you have provision for the padframe power.

add text in the middle of the box to say what the cell is.

create the layout for the main schematic without pads. (like this )
note: make sure it will fit inside a padframe! ...that is why you see the red poly outer border, used as a guide for the outer boundary for the cell layout. give the cell the same name as the main schematic, i.e, tpwsram1jan01u05

Make sure the cell size is about 95 percent of the size of the inside of the padframe area.
to do this, just draw a dummy padframe in an empty cell, create 4 metal1.blocking narrow rectangles at the 4 interior borders of the padframe to serve as guides for your cell. copy these to the clipboard, and place them in your cell as guides for your layout.

Use create-SDL from the adk palette to create the layout from the sdl viewpoint of your main schematic, (the other methods of creating a new cell dont seem to place the ports with overflows)

place all your components BEFORE placing ports

run Setup:SDL and set sdl portstyles setup/processport/default before placing any ports

from your schematic, make a list of where all your pads go and their names, or print out the schematic. you will need to refer to this for placing the ports
Place the ports at the perimeter of your cell.
Note, you will have to watch the bottom of ICstation to see the names of the current port being placed. (unfortunately they are randomly chosen) put them roughly where they belong on the padframe so they will be in the right area when you later add a padframe.
also, if you place the ports inside the blocking you may have trouble autorouting to them.
also, before placing ports, unselect everything in the schematic, then click place-port. (or select one port at a time and place it, but dont select ports plus schematic parts at the same time )

Place a metal1/via/metal2 via (4x4 metals) port directly under each port BEFORE doing any routing, otherwise you will have MAJOR problems

Stop, go back and put metal1/via/metal2 under all ports now!.

for each one of your ports, separately select the metalx.port and the metal1/via/metal2, and then use Connectivity:AddToPort to logically join metal1/via/metal2 to the port (as a rule you should later (after routing) add more metal than that small 4x4 area to the ports, such that they protrude out from the overall cell and protrude out from the final metal1.blocking and metal2.blocking layers that you will later add to your cells)

rearrange your cells so they are fairly closely spaced, or you will pay a nightmarish price later when you have to add filler.

after all this work, it would be wise to save this as tpwsram1jan01u05reva, so you could come back to this point at a later time if disaster strikes and you have to start over it would also be wise to save a new level of your design after each hour of work, tpwsram1jan01u05revx, so you could come back to an earlier level of work in case you need to recover from some horrid problem ... just make sure at the end that you save the final cell as tpwsram1jan01u05 and move all the intermediate garbage to some subdirectory "junk" when you get the final design. otherwise you will never be able to figure out which cell was used for your top layout ... spend the few minutes to clean up ...

Now would be a very wise time to fill in big empty spaces with a large metal1 and metal2 shapes (that you will later remove and replace with filler). this will prevent routes in that region and make adding filler a much easier task ... or you could just do it the hard way ...

route your cell

Now, place filler in all the gaps.
AMI05 requires minimum densities of certain layers. ( see mosis website for details) Poly is the one you must be most careful of, so add lots of poly to all your subcells and fill in the gaps on the main cell. Try for 20 percent poly visually. See the example in ~tpweldon/pub/ami05/ami05example.
Use the filler1, filler2, and filler3 cells (filler3 is biggest) as the basic filler unit. See here for a "peeked" view of a filler cell: filler3 cells These can be used to ground hand-drawn poly by connecting to the poly in the fillers. To add a filler cell, use the Add Cell command in the Object menu, and type in filler3 (these should automatically be in the search path for cells)
You can look at the filler cells in $ADK/lib/sdl/kli/newcells

Stop, go back and put the fillers in now!.
You must put the fillers into this cell, and not into the top-level cell with the padframes, because you must use LVS to make sure you didnt misplace the fillers and short circuit anything!

if you wisely used the large metal1 and metal2 shapes to save room for filler, delete those shapes and replace them with filler

cover your whole cell with metal1.blocking and metal2.blocking, with only your ports protruding out. if you cover the ports the router wont route to them because it is blocked! on the other hand anything you dont cover will be routed over -- creating short circuits ... the router doesnt see the metal in your cell!!!!

select your blocking layers, and use Object:change:aspect:both to make the blocking visible to the outside world ... otherwise the router wont see the blocking, and will route right through your cell!! short circuits galore

run drc

run IcTrace(M) to do LVS and see the report. Anything other than a smiley face is no good. Use your dummy schematic with all the grounds connected together for the schematic (and use the lvs viewpoint!)

save the layout in the top of the design directory (INSIDE THE DIRECTORY!)

make sure at the end that you save the final cell as tpwsram1jan01u05 (or whatever.. give it a meaningfull name) and move all the intermediate garbage (tpwsram1jan01u05x's) to some subdirectory "junk" when you get the final design. otherwise you will never be able to figure out which cell was used for your top layout ... spend the few minutes to clean up ...

now go back to your symbol, select the "box", and add the property PHY_COMP, and the name of your cell ... this is what keys mentor into looking for your cell when the symbol is in a schematic. check symbol, ignore the errors, save the symbol, recheck and get no errors.

Create a top-level schematic (with pads)

give the schematic the same name as the main schematic, except append "top", i.e., tpwsram1jan01u05top

create it with 40 pads (from ADK:pads menu) 10 pins at top, 10 bottom, 10 left, 10 right. (place all analog) then replace 2 with power ( VddPad and GndPad) so your padframe gets power.

number the pins (Property:modify) to PINXX where XX is 01 to 40, starting half-way up the right side and numbering consecutively counter clockwise.

Edit:Commands:Add:Electrical:Instance:SymbolbyPath to add your symbol (from the "main schematic")to the top-level schematic

wire up to the pins

Create the top-level layout (with pads)

give the top-level cell the same name as the top-level schematic, i.e., tpwsram1jan01u05top

use the "regular method" "Create" to create the cell, not "create-sdl"

use the layout viewpoint of your top-schematic (with the pads), flat heirarchy

place the component FIRST!

then ADK:generate padframe

you should get the padframe with the overflows,

move your cell to center it in the padframe

connect the overflows

run drc on the whole chip, ignore the 40 errors in the n-well of the bonding pads

Peek the whole top-level layout (peeked with pads) and check it.

save your cell

create tpwsram1jan01u05.gds from the ICsession:creategds2 palette .. please use the gds suffix!

ship it.

submit your gds file to mosis
and request that mosis NOT add filler.

if you did a good job, filler (fill-pattern) should not be needed, and you dont want to take any chances on what mosis automatic filler-adder might do to your design.

mosis will tell you if you dont have enough filler in your cell! ( see mosis website for details)
see the email reply from your mosis submission for the report on insufficient density of poly, etc ... if you dont get a complaint of insufficient density, you are ok.

fix and resubmit your design if you need more filler